D-33
SYSTEM REGISTER QUICK REFERENCE
D.30 IIRn
Interrupt ID
IIR0, IIR1
(read only) Expanded Addr:
ISA Addr:
Reset State:
IIR0 IIR1
F4FAH F8FAH
03FAH 02FAH
01H 01H
7 0
———— —IS2IS1IP#
Bit
Number Bit
Mnemonic Function
7–3 — Reserved. These bits are undefined.
2 IS2:1 Interrupt Source:
If an interrupt is pending (bit 0 = 0), these bits spe cify which status signal
caused the pending interru pt.
IS2 IS1 Interrupt Source
0 0 modem status signal*
0 1 transmitter buffer empt y signal
1 0 receive buffer full signal
1 1 receiver line status signal**
* When one of the modem input signals (CTS
n
#, DSR
n
#, RI
n
#, and
DCD
n
#) changes state, the modem status signal is activated.
** A framing error, overrun error, parity erro r, or break interrupt activates
the receiver line status signal.
Reading the modem status register clears the modem status signal.
Reading the IIR
n
register or writing to the transm it buffer register clears
the transmit buffer empty signal. Re ading the receive buffer register
clears the receive buffer full signal. Reading the receive buffer re gister or
the serial line status register clears the LSR
n
error bits, which clears the
receiver line status signal.
0 IP# Interrupt Pending:
This bit indicates whether an interrupt is pe nd in g.
0 = Interrupt i s pending
1 = No interrupt i s pending