D-59
SYSTEM REGISTER QUICK REFERENCE
D.59 SSIOCON1
SSIO Control 1
SSIOCON1
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F486H
—
C0H
7 0
TUE THBE TIE TEN ROE RHBF RIE REN
Bit
Number Bit
Mnemonic Function
7 TUE Transmit Underrun Error:
The transmitter sets this bit to i ndicate a transmit underrun erro r in the
TEN transfer mode. Clear this bit to clea r the error flag. If a one is written
to TUE, it is ignored and TUE retains its previous value.
6 THBE
(read only bit) Transmit Holding Buffer Empty:
The transmitter sets this bit when t he transmit buffer contents have bee n
transferred to the transmit shift register, indicating that the buffe r is now
ready to accept new data. Writing data to the transmit buffer clears THBE.
When this bit is clear, the buffer is not ready to accept any new data.
5 TIE Transmitter Interrupt Enable:
0 = Clearing th is bit prevents the Interrup t Control Unit from se nsing
when the transmit bu ffer is empty.
1 = Setting this bit connects th e transmit buffer empty inte rnal signal to
the Interrupt Control Un it.
4 TEN Transmitter Enable:
0 = Disables the tran smitter.
1 = Enables the transmitter.
3 ROE Receive Overflow Error:
The receiver sets this bit to indicate a receiver overflow error. Write zero
to this bit to clear the flag.
If a one is written to ROE, the one is ignored and ROE retains its previous
value.
2 RHBF
(read only bit) Receive Holding Buffer Full:
The receiver sets this bit when the re ceive shift register contents have
been transferred to the receive b uffer.
Reading the buffer clears this bit.
1 RIE Receive Interrupt Enable:
0 = Clearing th is bit prevents the Interrup t Control Unit from se nsing
when the receive buffer is fu ll.
1 = Setting this bit connects th e receiver buffer full internal signal to the
Interrupt Control Unit.
0 REN Receiver Enable:
0 = Clearing this bit disables the receiver.
1 = Setting this bit enabl es the receiver.