17-9
WATCHDOG TIMER UNIT
Figure 17-3. WDT Status Register (WDTSTATUS)WDT Status
WDTSTATUS
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F4CAH
—
00H
7 0
WDTEN — — — — — BUSMON CLKDIS
Bit
Number Bit
Mnemonic Function
7 WDTEN Watchdog Mode Enabled:
This read-only bit indicates whether watchdog mode is e nabled. Only a
lockout sequence can set this bit and only a device reset can clear it.
0 = Watchdog mode d isabled
1 = Watchdog mode enabled
6–2 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify thes e bits.
1 BUSMON Bus Monitor Enable:
0 = Disables bus m onitor mode
1 = Enables bus monitor mode
Read this bit to determine the curre nt status. A lockout sequence clears
BUSMON and prevents writes to the WDTSTATUS register.
0 CLKDIS Clock Disable:
Write to this bit to stop or restart the clock to the WDT; read it to
determine the current clock status. A lockout seq uence clears CLKDIS
and prevents writing to this register.
0 = Clock ena bled
1 = Processor clock (freque ncy=CLK2/2) disabled (stopped)