Intel 386 Table A-2. Description of Signals Available at the Device Pins (Sheet 6 of 6)

A-7

SIGNAL DESCRIPTIONS

TMS I Test Mode Select:

Controls the sequence of the test-lo gic unit’s TAP controller

states. Sampled on the rising edge of TC K.

—

TRST# ST Test Reset:

Resets the test-logic unit’s TAP controller. Asynchronously

clears the data registers and initializes the instruction

—

TXD1

TXD0 O Transmit Da ta:

Transmits serial data from the corresponding SIO channel.

DACK1#

P2.6

UCS# O Upper Chi p-select:

Activated when the address of a memory or I/O bus cycle is

within the address region programme d by the user.

—

VCC P System Power:

Provides the nominal DC supply input. Connected

externally to a VCC board plane.

—

VSS G System Ground:

Provides the 0 volt connection from wh ich all inputs and

outputs are measured. Connected exte rnally to a ground

board plane.

—

WDTOUT O Watchdog Timer Output:

Indicates that the watchdog timer has expired.

—

W/R# O Write/Read:

Indicates whether the current bus cycle is a write c ycle or a

read cycle.

—

WR# O Write Enab le:

Indicates that the current bus cycle is a write cycle.

—

Table A-2. Description of Signals Available at the Device Pins (Sheet 6 of 6)

Signal Type Name and Description Multiplexed With

(Alternate

Function)