17-11
WATCHDOG TIMER UNIT
Figure 17-5. Power Control Register (PWRCON)Power Control Register
PWRCON
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F800H
—
00H
7 0
— — — — WDTRDY HSREADY PC1 PC0
Bit
Number Bit
Mnemonic Function
7–4 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
3 WDTRDY Watch Dog Timer Ready:
0 = An external READY must be generated to terminate the cy cle when
the WDT times out in Bus Monitor Mode.
1 = Internal logic generates READY# to terminate the cycle when the
WDT times out in Bus Monitor Mode.
2 HSREADY Halt/Shutdown Ready:
0 = An external ready must be generated to terminate a HALT/Shutdown
cycle.
1 = Internal logic generates R EADY# to terminate a HALT/Shutdown
cycle.
1–0 PC1:0 Power Control:
Program these bits, then execute a HALT instruction. The device enters
the programmed mode when READY# (in ternal or external) terminates
the halt bus cycle. When these bits have eq ual values, the HALT
instruction causes a normal halt and the d evice remains in active mode.
PC1 PC0
0 0 active mode
1 0 idle mode
01powerdown mode
1 1 active mode