Intel 386 Figure 12-30. DMA Group Channel Mask Register (DMAGRPMSK)

12-45
DMA CONTROLLER
Figure 12-30. DMA Group Channel Mask Register (DMAGRPMSK)
DMA Group Channel Mask
DMAGRPMSK
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F00FH
000FH
03H
7 0
———— ——HRM1HRM0
Bit
Number Bit Mnemonic Function
7–2 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify thes e bits.
1 HRM1 Hardware Request Mask 1:
0 = Channel 1’s hardware requests are not masked.
1 = Masks (disables) chann el 1’s hardware requests. When this bit is
set, channel 1 can still receive software requests.
0 HRM0 Hardware Request Mask 0:
0 = Channel 0’s hardware requests are not masked.
1 = Masks (disables) chann el 0’s hardware requests. When this bit is
set, channel 0 can still receive software requests.