Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
D-28
D.23 ICW1 (MASTER AND SLAVE)Initialization Command Word 1
ICW1 (master and slave)
(write only) Expanded Addr:
ISA Addr:
Reset State:
master slave
F020H F0A0H
0020H 00A0H
XXH XXH
7 0
0 0 0 RSEL1 LS 0 0 1
Bit
Number Bit
Mnemonic Function
7–5 — Clear these bits to guaran tee device operation.
4 RSEL1 Regi ster Select 1 (Also see OCW2 and OCW3) :
ICW1, OCW2, and OCW3 are accessed through the same addresses.
0 = OCW2 or OCW3 is a ccessed (Figure 9-13 and Figure 9-15).
1 = ICW1 register is a ccessed.
3 LS Level/Edge Sensitive:
0 = Selects edge- triggered IR input signals.
1 = Selects level-sensitive IR input signals.
All internal peripherals interface with the 82C5 9A s in edge-triggered
mode only. This is compatible with the PC/AT bus specification. Each
source signal initiates an interru pt request by making a low-to-h igh
transition. External peripherals interface with the 8259As in edge-
triggered or level-sensitive mo de. The modes are selected for th e
device, not for individual interrup ts.
NOTE: If an internal peri pheral interrupt is used, th e 8259A that the
interrupt is connected to must be prog rammed for edge-triggered
interrupts.
2–1 — Clear these bits to guaran tee device operation.
0 — Set thi s bi t to gua ran tee device operation.
NOTE: The 82C59A must be initialized b efore it can be used. After reset, the 82C59A register states are
undefined. The 82C59A modules must be in itialized before the IF flag in the core FLAG r egister is
set. All peripherals that use inte rrupts connected to the ICU must be i nitialized before initializing
the ICU.