Intel 386 Table 12-3. DMA Registers (Sheet 3 of 3)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

12-30

DMACHR

(write only) F019H — DMA Chaining:

Enables chaining buffer-transfer m ode for a specified

channel.

DMAIEN

(read/write) F01CH — DMA Interrupt Enable:

Connects the channel transfer complete status

signals to the interrupt request out put (DMAINT).

DMAIS

(read only) F019H — DMA Interrupt Status:

Indicates which signal generate d an interrupt request:

channel 0 transfer complete, channel 1 transfer

complete, channel 0 chaining, or ch annel 1 chaining

status.

DMAOVFE

(read/write) F01DH — DMA Overflow Enable:

Included for 8237A compatibility. Controls wheth er all

26 bits or only the lower 16 b its of the requester and

target addresses are incremented or decremented

during buffer transfers. Controls whether the byte

count is 24 bits or 16 bits.

Table 12-3. DMA Registers (Sheet 3 of 3)

Address PC/AT*

Address Description