Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
12-36
12.3.6 Status Register (DMASTS)Use DMASTS to check the status of the channe ls individually. The DMA sets bits in this registerto indicate that a channel has a hardware request pending or that a channel’s byte count has ex-pired.

Figure 12-23. DMA Status Register (DMASTS)

DMA Status
DMASTS
(read only)
Expanded Addr:
ISA Addr:
Reset State:
F008H
0008H
00H
7 0
— — R1 R0 — — TC1 TC0

Bit

Number Bit

Mnemonic Function

7–6 — Reserved. These bits are undefined.
5 R1 Request 1:
When set, this bit indicates that channel 1 has a hardware request
pending. When the request is removed, this bit is cleared.
4 R0 Request 0:
When set, this bit indicates that channel 0 has a hardware request
pending. When the request is removed, this bit is cleared.
3–2 — Reserved. These bits are undefined.
1 TC1 Transfer Complete 1:
When set, this bit indicates that channe l 1 has co mp le te d a buffe r
transfer (either its byte count expire d or it received an EOP# input).
Reading this register clears this bit an d clears TC1 in DMAIS.
0 TC0 Transfer Complete 0:
When set, this bit indicates that channe l 0 has co mp le te d a buffe r
transfer (either its byte count expire d or it received an EOP# input).
Reading this register clears this bit an d clears TC0 in DMAIS.