6-17
BUS INTERFACE UNIT
4. The WR# signal can be deasserted in two ways.
•Early Ready: WR# is deasserted at the rising edge of CLK2 in the middle of the T2
state, after any wait states programmed in the Chip-select Unit have expired.
At the rising edge of PH2, READY# is sampled. If it is found active, WR# is
synchronously deasserted in the middle of T2, driven inactive by the risi ng edge of
the PH2 clock. The write cycle is then terminated at the end of the T2 state.
NOTE
When READY# is generated by the processor (e.g., when the Chip-sele ct Unit
generates it), then the write cycle is always a n Early Ready cycle.
•Late Ready: When READY# goes low after the rising edge of PH2 of the T2 state
(after the wait-states, if any are programmed in the Chip-select Unit, have expired),
WR# is asynchronously deasserted as soon as READY# is asserted (after a sm all
delay caused by the logic). The write cycle is then terminated at the end of the T2
state.
The WR# signal operates in this manner to ensure sufficient address and chip-select hold
time during write cycles (required by many memory and I/O devices). In the first case, the
address and chip-select hold time is approximately one CLK2 cycle.
5. When READY# is high, wait-states are added (additional T2 states for nonpipelined
cycles) until READY# is sampled low. READY# is sampled in each T2 state (starting at
the rising edge of PH2) to deassert the WR# signal appropriately, and at the end of each T2
state (at the falling edge of PH2) to terminate the cycle.
6. Once READY# is sampled low, the write cycle terminates. If a new bus cycle is pending,
it begins on the next T-state.