Intel 386 Even if bus cycles are pipelined, the minimum clock numbers are guaranteed.

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
7-6
Figure 7-2. SMIACT# Latency
NOTE
Even if bus cycles are pipelined, the minimum clock numbers are guaranteed.
A2512-02
CLKOUT
T1 T2
CLK2
ADS#
SMI#
SMIACT#
READY#
B D
A
C
Normal State State Save, SMM Handler,
State Restore Normal State
A = 1 CLK min, B = 20 CLK min, C = 16 CLK min, D = 4 CLK min