Intel® Server Board SDS2Glossary

Glossary

This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.

Term

Definition

 

 

ACPI

Advanced Configuration and Power Interface

 

 

ASIC

Application specific integrated circuit

 

 

BIOS

Basic input/output system

 

 

BIST

Built-in self test

 

 

BMC

Baseboard Management Controller

 

 

Bridge

Circuitry connecting one computer bus to another, allowing an agent on one to access the other.

 

 

Byte

8-bit quantity.

 

 

BYO

Build your own

 

 

CIOB

PCI 64-bit hub

 

 

CMOS

In terms of this specification, this describes the PC-AT compatible region of battery-backed 128

 

bytes of memory, which normally resides on the baseboard.

 

 

CSB5

Legacy I/O controller hub

 

 

EEPROM

Electrically erasable programmable read-only memory

 

 

EMP

Emergency management port

 

 

EPS

External Product Specification

 

 

FRB

Fault resilient booting

 

 

FRU

Field replaceable unit

 

 

GB

1024 MB.

 

 

GPIO

General Purpose I/O

 

 

GTL

Gunning Transceiver Logic

 

 

HSC

Hot-swap controller

 

 

Hz

Hertz (1 cycle/second)

 

 

I2C

Inter-integrated circuit bus

IA

Intel® architecture

ICMB

Intelligent Chassis Management Bus

 

 

IERR

Internal error

 

 

IPMB

Intelligent Platform Management Bus

 

 

IPMI

Intelligent Platform Management Interface

 

 

ITP

In-target probe

 

 

KB

1024 bytes.

 

 

LAN

Local area network

 

 

LPC

Low pin count

 

 

LUN

Logical unit number

 

 

MAC

Media Access Control

 

 

MB

1024 KB

 

 

Ms

milliseconds

 

 

Revision 1.2

I

Order Number:

A85874-002

Page 138
Image 138
Intel SDS2 manual Term Definition