Intel SDS2 manual CIOB20 Champion I/O Bridge, 3 CSB5 South Bridge, PCI Bus P64-B I/O Subsystem

Processor and Chipset Intel® Server Board SDS2

3.3.2CIOB20 Champion I/O Bridge

The Champion I/O Bridge (CIOB) is a 352-pin ball-grid array device and provides an integrated I/O bridge that provides a high-performance data flow path between the IMBus and the 64-bit I/O subsystem. This subsystem supports peer 64-bit PCI segments. Because it has multiple PCI interfaces, the CIOB can provide large and efficient I/O configurations. The CIOB functions as the bridge between the IMBus and the multiple 64-bit PCI I/O segments.

The IMBus interface can support 512 MB/s of data bandwidth in both the upstream and downstream direction simultaneously.

The internal PCI arbiter implements the Least Recently used algorithm to grant access to requesting masters.

3.3.2.1PCI Bus P64-B I/O Subsystem

P64-B supports two 64-bit, 66-MHz 3.3V full-length PCI slots.

3.3.2.2PCI Bus P64-C I/O Subsystem

P64-C supports the following embedded devices and connectors:

∙Dual Channel Wide Ultra160 SCSI controller: Adaptec* AIC-7899W

∙Two 64-bit, 66-MHz 3.3V full length PCI Slots

3.3.3CSB5 South Bridge

Please refer to Section 4.5 for information on CSB5.

10	Revision 1.2
Order Number:	A85874-002