Intel SDS2 manual Cpu He-Sl

Revision 1.2

Order Number: A85874-002

71

14.318 MHz

SDRAM

REGISTER 1

SDRAM

133 MHz

133 MHz

REGISTER 2

133 MHz

133 MHz

133 MHz

133 MHz

SDRAM 1

Figure

HOST CLK

133 MHz

SDRAM 2

133 MHz

SDRAM 3

CPU 1

CPU 2

HE-SL

SDRAM

8.

CNBDCLKIN

CLK PLL

133 MHz

SDRAM 4

SDS2

16 MHz

133 MHz

SDRAM 5

16 MHz

APIC CLK

Server

16 MHz

133 MHz

SDRAM 6

48 MHz

133 MHz

48 MHz

AGPFBCLK

133 MHz

48 MHz

CSB5

133 MHz

Board

14 MHz

14 MHz

CNBDCLKFB

14 MHz

PLLCLKFB0

Clock

CNBRDCLK

SIO

25 MHz

Generation/Distribution

33 MHz

32 KHz

33 MHz

BUFFER

BMC

40 MHz

VGA

NIC 1

25 MHz

NIC 2

33 MHz

PCI 33MHz CLK

40 MHz

33 MHz

PCI SLOT 3

33 MHz

PCI 33MHz

33 MHz

PCI SLOT 4

66 MHz

U160 SCSI

CLK

Diagram

33 MHz

66 MHz

33 MHz

IRQ 0

IRQ 1

PCI

66 MHz

PCI SLOT 5

66MHz CLK

66 MHz

BUFFER

66 MHz

PCI SLOT 6

33 MHz

cPLD

33 MHz

CIOB

PCI 66MHz CLK

66 MHz

66 MHz

66 MHz

PCI SLOT 1

PCI

66MHz CLK

BUFFER

66 MHz

PCI SLOT 2

66 MHz

Intel® Server Board SDS2

Clock/Voltage Generation and Distribution