Table of Contents Intel® Server Board SDS2
Revision 1.2
Order Number: A85874-002
iv
Table of Contents
1. Introduction .............................................................................................................................1
2. Architecture.............................................................................................................................2
3. Processor and Chipset..........................................................................................................4
3.1 Processors.........................................................................................................................4
3.1.1 Processor Voltage Regulator Module (VRM)................................................................6
3.2 Memory Subsystem............................................................................................................6
3.2.1 Memory Configuration...................................................................................................6
3.2.2 I2C Bus..........................................................................................................................8
3.3 Chipset................................................................................................................................8
3.3.1 CNB20HE-SL Champion North Bridge.........................................................................9
3.3.2 CIOB20 Champion I/O Bridge ....................................................................................10
3.3.3 CSB5 South Bridge.....................................................................................................10
4. I/O Subsystem........................................................................................................................11
4.1 PCI Subsystem.................................................................................................................11
4.1.1 32-bit, 33-MHz PCI Subsystem ..................................................................................11
4.1.2 64-bit, 66-MHz PCI Subsystem ..................................................................................12
4.2 Ultra160 SCSI...................................................................................................................14
4.3 Video Controller ................................................................................................................14
4.3.1 Video Modes................................................................................................................14
4.4 Network Interface Controller (NIC)....................................................................................15
4.4.1 NIC Connector and Status LEDs................................................................................16
4.5 CSB5 South Bridge (PCI-to-LPC Bridge, IDE, USB).......................................................16
4.5.1 PCI Bus Interface........................................................................................................16
4.5.2 PCI Bus Master IDE Interface.....................................................................................16
4.5.3 USB Interface..............................................................................................................17
4.5.4 Compatibility Interrupt Control.....................................................................................17
4.5.5 APIC ............................................................................................................................17
4.5.6 Power Management....................................................................................................17
4.5.7 General Purpose Input and Output Pins.....................................................................17
4.6 Chipset Support Components..........................................................................................18
4.6.1 Super I/O.....................................................................................................................18