EPCI/PMC TechnologyOverview E
PCI/PMC Technology
Intel® Corporation’s Architecture Lab, along with leading computer vendors (the PCI SIG), designed the Peripheral Component Interconnect (PCI) bus as the next generation I/O expansion bus. Its predecessors were the ISA, EISA, and MCA buses. The PCI bus is a high-performance bus found in systems ranging from low-end PCs to high-end servers.
PCI was developed to overcome the bottlenecks associated with traditional 16-bit expansion slots operating at 8 MHz, or, essentially, 5 megabytes per second. The result was a local bus system capable of transferring 32 bits of data at 33 MHz for a maximum data transfer rate of 132 MBps. The PCI Local Bus takes peripherals off the I/O bus and connects them together with the CPU and the memory subsystem. This provides a wider, faster pathway for data, which is especially important for servers, graphic-intensive software, high-speed networks, and other high-performance peripherals.
Features of the PCI Local Bus architecture include:
•Processor-independent bridge between the CPU and high-speed peripherals that serves as traffic controller between buses
•32-bit memory addressing for CPU, Direct Memory Access (DMA) devices, and bus masters
•32-bit data transfers at 33 MHz for CPU, DMA, and bus master devices
•132 MBps maximum data transfer rate
•Data are written and read from peripherals in linear bursts at every clock cycle
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