Toshiba PORTG M500 2.4 System Board Troubleshooting 2 Troubleshooting Procedures , Table 2-4 Debug port (Boot mode) error status (3/10)

2.4 System Board Troubleshooting 2 Troubleshooting Procedures
PORTÉGÉ M500 Maintenance Manual (960-559) [CONFIDENTIAL] 2-25
Table 2-4 Debug port (Boot mode) error status (3/10)
D port status Inspection items Details
IRT_START
Process of cache control for
HyperThreading
F100H
Prohibition of cache
Initialization of MCHM
Initialization of ICH4M.D31.Func0
Initialization of ICH4M.D31.Func1
Initialization of USB.Func0,1,2,7
Initialization of ICH4M.D31.Func3
Initialization of ICH4M.D31.Func5
Initialization of H/W (before DRAM
recognition)
Initialization of FLUTE
Initialization of PIT channel 1 (Setting the refresh interval to “30μs”)
IRT_INI_SPREG_END
Check of DRAM type and size
(at cold boot) When unsupported memory is connected, becoming HLT after beep sound (HLT when
DRAM size is 0)
F101H
SM-RAM stack area test HLT When it can not be used as a stack
Cache configuration
Cache permission (L1/L2 Cac he)
CMOS access test (at cold boot) (HLT when an error is detected)
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status (Setting of boot status and IRT busy flag, The rest
bits are 0)
Storing DRAM size in CMOS
F102H
Cache configuration
F103H IRT_RSM_BRANCH
Not resume when a CMOS error occurred
Not resume when resume status code is not set
Resume error check
Resume branch (at cold boot)
S3 returning error (ICH)
Resume error F170 RSM_UNKNOW N_ERR