Intel Itanium 2 Processor manual STBn70# and STBp70# I/O, Tdo O, Thrmtrip# O

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Signals Reference

A.1.59 STBn[7:0]# and STBp[7:0]# (I/O)

STBp[7:0]# and STBn[7:0]# (and DRDY#) are used to transfer data at the 2x transfer rate in lieu of BCLKp. They are driven by the data transfer agent with a tight skew relationship with respect to its corresponding bus signals, and are used by the receiving agent to capture valid data in its latches. This functions like an independent double frequency clock constructed from a falling edge of either STBp[7:0]# or STBn[7:0]#. The data is synchronized by DRDY#. Each strobe pair is associated with 16 data bus signals and two ECC signals as shown in Table A-11.

Table A-11. STBp[7:0]# and STBn[7:0]# Associations

Strobe Bits

Data Bits

ECC Bits

 

 

 

STBp[7]#, STBn[7]#

D[127:112]#

DEP[15:14]#

 

 

 

STBp[6]#, STBn[6]#

D[111:96]#

DEP[13:12]#

 

 

 

STBp[5]#, STBn[5]#

D[95:80]#

DEP[11:10]#

 

 

 

STBp[4]#, STBn[4]#

D[79:64]#

DEP[9:8]#

 

 

 

STBp[3]#, STBn[3]#

D[63:48]#

DEP[7:6]#

 

 

 

STBp[2]#, STBn[2]#

D[47:32]#

DEP[5:4]#

 

 

 

STBp[1]#, STBn[1]#

D[31:16]#

DEP[3:2]#

 

 

 

STBp[0]#, STBn[0]#

D[15:0]#

DEP[1:0]#

 

 

 

A.1.60

TCK (I)

 

The Test Clock (TCK) signal provides the clock input for the IEEE 1149.1 compliant TAP.

A.1.61

TDI (I)

The Test Data In (TDI) signal transfers serial test data into the Itanium 2 processor. TDI provides the serial input needed for IEEE 1149.1 compliant TAP.

A.1.62 TDO (O)

The Test Data Out (TDO) signal transfers serial test data out from the Itanium 2 processor. TDO provides the serial output needed for IEEE 1149.1 compliant TAP.

A.1.63 THRMTRIP# (O)

The Thermal Trip (THRMTRIP#) signal protects the Itanium 2 processor from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. Data will be lost if the processor goes into thermal trip (signaled to the system by the assertion of the THRMTRIP# signal). Once THRMTRIP# is asserted, the platform must assert RESET# to protect the physical integrity of the processor.

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Datasheet

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Contents Datasheet Intel Itanium 2 ProcessorDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR#106 Revision History Revision No Description DateProduct Features Intel Itanium 2 ProcessorDatasheet Overview Processor Abstraction LayerState of Data Mixing Processors of Different Frequencies and Cache SizesTerminology Reference Documents Title Document NumberIntroduction System Bus Signals System Bus Power PinsSignal Groups Itanium 2 Processor System BusGroup Name Signals Signal DescriptionsItanium 2 Processor System Bus Signal Groups Symbol Parameter Core Minimum Typ Maximum Unit Package SpecificationsItanium 2 Processor Package Specifications Signal Specifications Itanium 2 Processor Power Supply SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum UnitAGTL+ Signals DC Specifications Sheet 2 Power Good Signal DC SpecificationsSystem Bus Clock Differential Hstl DC Specifications TAP Connection DC SpecificationsSMBus DC Specifications Lvttl Signal DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum Unit11. SMBus AC Specifications Minimum Typ MaximumMaximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2Overshoot/Undershoot Pulse Duration Activity FactorReading Overshoot/Undershoot Specification Tables VctermParameter Description Specification Units Absolute Pulse Duration nsOver AF = 1 Shoot0143 Wired-OR Signals 0513 Power Pod Connector Signals 22. Itanium 2 Processor Power Pod Connector SignalsGroup Name Signals Power Pod Connector Absolute23. Processor Core Voltage Identification Code1 VID2 VID1 VID0State Transition Ramp Rate Comment 24. Processor Power StatesItanium 2 Processor System Bus Clock and Processor Clocking 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17#System Bus Reset and Configuration Timings for Cold Reset Recommended Connections for Unused Pins 26. Connection for Unused Pins Sheet 1Pins/Pin Groups Recommended TAP Signals26. Connection for Unused Pins Sheet 2 System Management SignalsLvttl Power Pod Signals Reserved PinsPinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal NamePin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/OutputPin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 LocationPin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor PackageProcessor Substrate UnitsItanium 2 Processor Package Power Tab Processor Bottom-Side Marking Package MarkingProcessor Top-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal AlertCase Temperature Case Temperature SpecificationSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signals System Management Interface Signal DescriptionsSignal Name Pin Count Description System Management BusSystem Management Feature Specifications SMBus Device Addressing 9XhProcessor Information ROM Format Sheet 1 Processor Information ROMEeprom SMBus Addressing on the Itanium 2 Processor Cache Processor Information ROM Format Sheet 2Offset Function Examples Section Bits Features Processor Information ROM Format Sheet 3Offset Function Examples Section Bits Package Part NumbersOther Scratch EepromProcessor Information ROM Format Sheet 4 Thermal Sensing Device Current Address Read SMBus PacketRandom Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions 13. Command Byte Bit Assignment Register Command Reset State FunctionThermal Sensing Device Registers Thermal Reference RegistersConfiguration Register 15. Thermal Sensing Device Configuration RegisterThermal Limit Registers Status Register16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate HzConversion Rate Register Alphabetical Signals Reference Table A-2. Effective Memory Type Signal Encoding ATTR30# I/OBCLKp/BCLKn 8 BE70# I/OBERR# I/O Table A-3. Special Transaction Encoding on Byte EnablesSpecial Transaction Byte Enables70# BINIT# I/O 11 BNR# I/O12 BPM50# I/O BPRI#Table A-6. BR30# Signals and Agent IDs Bus Signal Agent 0 Pins Agent 3 PinsBREQ30# I/O Pin SampledCCL# I/O D1270# I/O# I/O DBSYC1# ODBSYC2# O DEFER#24 DEN# I/O 25 DEP150# I/O27 DPS# I/O DRDY# I/ODRDYC1# O DRDYC2# O33 FCL# I/O FERR# OHIT# I/O and HITM# I/O ID90#IP10# LEN20# I/OTable A-9. Length of Data Transfers LEN20#LINT10 OWN# I/OPMI# REQ50# I/OTransaction REQa50# REQb50# RESET#52 RP# I/O RS20# RSP#SBSYC1# O SBSYC2# OSTBn70# and STBp70# I/O TDO OTHRMTRIP# O Table A-11. STBp70# and STBn70# AssociationsSignal Summaries Table A-12. Output Signals Sheet 1Name Active Level Clock Signal Group TND# I/OName Active Level Clock Signal Group Qualified Table A-12. Output Signals Sheet 2Table A-13. Input Signals Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver108