Intel Itanium 2 Processor manual Pin/Signal Information Sorted by Pin Location Sheet 12

Page 64

Pinout Specifications

Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 12 of 15)

Pin Name

System Bus

Pin

Input/Output

Notes

Signal Name

Location

 

 

 

 

 

 

 

 

A035#

AA35#/ATTR3#

Y18

IN/OUT

 

 

 

 

 

 

GND

GND

Y19

IN

 

 

 

 

 

 

A039#

AA39#/AB39#

Y20

IN/OUT

 

 

 

 

 

 

GND

GND

Y21

IN

 

 

 

 

 

 

A049#

AA49#/AB49#

Y22

IN/OUT

 

 

 

 

 

 

GND

GND

Y23

IN

 

 

 

 

 

 

A043#

AA43#/AB43#

Y24

IN/OUT

 

 

 

 

 

 

GND

GND

Y25

IN

 

 

 

 

 

 

GND

GND

AA02

IN

 

 

 

 

 

 

ID3#

IDA3#/IDB3#

AA03

IN

 

 

 

 

 

 

A011#

AA11#/BE3#

AA05

IN/OUT

 

 

 

 

 

 

DRDY0#

DRDY_C1#

AA07

OUT

 

 

 

 

 

 

DBSY0#

DBSY_C1#

AA09

OUT

 

 

 

 

 

 

A023#

AA23#/DID7#

AA11

IN/OUT

 

 

 

 

 

 

SBSY0#

SBSY_C1#

AA13

OUT

 

 

 

 

 

 

BINIT#

BINIT#

AA15

IN/OUT

 

 

 

 

 

 

A033#

AA33#/ATTR1#

AA17

IN/OUT

 

 

 

 

 

 

DBSY1#

DBSY_C2#

AA19

OUT

 

 

 

 

 

 

GND

GND

AA20

IN

 

 

 

 

 

 

DRDY1#

DRDY_C2#

AA21

OUT

 

 

 

 

 

 

AP1#

AP1#

AA23

IN/OUT

 

 

 

 

 

 

GND

GND

AA24

IN

 

 

 

 

 

 

AP0#

AP0#

AA25

IN/OUT

 

 

 

 

 

 

GND

GND

AB01

IN

 

 

 

 

 

 

ID1#

IDA1#/IP1#

AB02

IN

 

 

 

 

 

 

GND

GND

AB03

IN

 

 

 

 

 

 

ID5#

IDA5#/IDB5#

AB04

IN

 

 

 

 

 

 

GND

GND

AB05

IN

 

 

 

 

 

 

ID9#

IDA9#/IDB9#

AB06

IN

 

 

 

 

 

 

GND

GND

AB07

IN

 

 

 

 

 

 

RS2#

RS2#

AB08

IN

 

 

 

 

 

 

GND

GND

AB09

IN

 

 

 

 

 

 

HIT#

HIT#

AB10

IN/OUT

 

 

 

 

 

 

GND

GND

AB11

IN

 

 

 

 

 

 

HITM#

HITM#

AB12

IN/OUT

 

 

 

 

 

 

GND

GND

AB13

IN

 

 

 

 

 

 

DEFER#

DEFER#

AB14

IN

 

 

 

 

 

 

GND

GND

AB15

IN

 

 

 

 

 

 

N/C

 

AB16

 

 

 

 

 

 

 

GND

GND

AB17

IN

 

 

 

 

 

 

BR2#

BREQ2#

AB18

IN

 

 

 

 

 

 

64

Datasheet

Image 64
Contents Datasheet Intel Itanium 2 ProcessorDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR#106 Revision History Revision No Description DateProduct Features Intel Itanium 2 ProcessorDatasheet Overview Processor Abstraction LayerTerminology Mixing Processors of Different Frequencies and Cache SizesState of Data Reference Documents Title Document NumberIntroduction System Bus Signals System Bus Power PinsSignal Groups Itanium 2 Processor System BusItanium 2 Processor System Bus Signal Groups Signal DescriptionsGroup Name Signals Itanium 2 Processor Package Specifications Package SpecificationsSymbol Parameter Core Minimum Typ Maximum Unit Signal Specifications Itanium 2 Processor Power Supply SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum UnitAGTL+ Signals DC Specifications Sheet 2 Power Good Signal DC SpecificationsSystem Bus Clock Differential Hstl DC Specifications TAP Connection DC SpecificationsSMBus DC Specifications Lvttl Signal DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum Unit11. SMBus AC Specifications Minimum Typ MaximumMaximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2Overshoot/Undershoot Pulse Duration Activity FactorReading Overshoot/Undershoot Specification Tables VctermParameter Description Specification Units Absolute Pulse Duration nsOver AF = 1 Shoot0143 Wired-OR Signals 0513 Power Pod Connector Signals 22. Itanium 2 Processor Power Pod Connector SignalsGroup Name Signals Power Pod Connector Absolute23. Processor Core Voltage Identification Code1 VID2 VID1 VID0Itanium 2 Processor System Bus Clock and Processor Clocking 24. Processor Power StatesState Transition Ramp Rate Comment 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17#System Bus Reset and Configuration Timings for Cold Reset Recommended Connections for Unused Pins 26. Connection for Unused Pins Sheet 1Pins/Pin Groups Recommended TAP Signals26. Connection for Unused Pins Sheet 2 System Management SignalsLvttl Power Pod Signals Reserved PinsPinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal NamePin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/OutputPin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 LocationPin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor PackageProcessor Substrate UnitsItanium 2 Processor Package Power Tab Processor Top-Side Marking Package MarkingProcessor Bottom-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal AlertCase Temperature Case Temperature SpecificationSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signals System Management Interface Signal DescriptionsSignal Name Pin Count Description System Management BusSystem Management Feature Specifications SMBus Device Addressing 9XhEeprom SMBus Addressing on the Itanium 2 Processor Processor Information ROMProcessor Information ROM Format Sheet 1 Offset Function Examples Section Bits Processor Information ROM Format Sheet 2Cache Features Processor Information ROM Format Sheet 3Offset Function Examples Section Bits Package Part NumbersProcessor Information ROM Format Sheet 4 Scratch EepromOther Thermal Sensing Device Current Address Read SMBus PacketRandom Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions 13. Command Byte Bit Assignment Register Command Reset State FunctionThermal Sensing Device Registers Thermal Reference RegistersConfiguration Register 15. Thermal Sensing Device Configuration RegisterThermal Limit Registers Status RegisterConversion Rate Register Register Contents Conversion Rate Hz16. Thermal Sensing Device Conversion Rate Register Alphabetical Signals Reference Table A-2. Effective Memory Type Signal Encoding ATTR30# I/OBCLKp/BCLKn 8 BE70# I/OSpecial Transaction Byte Enables70# Table A-3. Special Transaction Encoding on Byte EnablesBERR# I/O BINIT# I/O 11 BNR# I/O12 BPM50# I/O BPRI#Table A-6. BR30# Signals and Agent IDs Bus Signal Agent 0 Pins Agent 3 PinsBREQ30# I/O Pin SampledCCL# I/O D1270# I/O# I/O DBSYC1# ODBSYC2# O DEFER#24 DEN# I/O 25 DEP150# I/O27 DPS# I/O DRDY# I/ODRDYC1# O DRDYC2# O33 FCL# I/O FERR# OHIT# I/O and HITM# I/O ID90#IP10# LEN20# I/OTable A-9. Length of Data Transfers LEN20#LINT10 OWN# I/OPMI# REQ50# I/O52 RP# I/O RESET#Transaction REQa50# REQb50# RS20# RSP#SBSYC1# O SBSYC2# OSTBn70# and STBp70# I/O TDO OTHRMTRIP# O Table A-11. STBp70# and STBn70# AssociationsSignal Summaries Table A-12. Output Signals Sheet 1Name Active Level Clock Signal Group TND# I/OTable A-13. Input Signals Table A-12. Output Signals Sheet 2Name Active Level Clock Signal Group Qualified Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver108