Intel Itanium 2 Processor manual Pin/Signal Information Sorted by Pin Location Sheet 5

Page 57

Pinout Specifications

Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 5 of 15)

Pin Name

System Bus

Pin

Input/Output

Notes

Signal Name

Location

 

 

 

 

 

 

 

 

VCTERM

VCTERM

G24

IN

 

 

 

 

 

 

D107#

D107#

G25

IN/OUT

 

 

 

 

 

 

D011#

D11#

H02

IN/OUT

 

 

 

 

 

 

GND

GND

H03

IN

 

 

 

 

 

 

D012#

D12#

H04

IN/OUT

 

 

 

 

 

 

GND

GND

H05

IN

 

 

 

 

 

 

D009#

D09#

H06

IN/OUT

 

 

 

 

 

 

GND

GND

H07

IN

 

 

 

 

 

 

D042#

D42#

H08

IN/OUT

 

 

 

 

 

 

GND

GND

H09

IN

 

 

 

 

 

 

D032#

D32#

H10

IN/OUT

 

 

 

 

 

 

GND

GND

H11

IN

 

 

 

 

 

 

D046#

D46#

H12

IN/OUT

 

 

 

 

 

 

GND

GND

H13

IN

 

 

 

 

 

 

D075#

D75#

H14

IN/OUT

 

 

 

 

 

 

GND

GND

H15

IN

 

 

 

 

 

 

D076#

D76#

H16

IN/OUT

 

 

 

 

 

 

GND

GND

H17

IN

 

 

 

 

 

 

D077#

D77#

H18

IN/OUT

 

 

 

 

 

 

GND

GND

H19

IN

 

 

 

 

 

 

D111#

D111#

H20

IN/OUT

 

 

 

 

 

 

GND

GND

H21

IN

 

 

 

 

 

 

D105#

D105#

H22

IN/OUT

 

 

 

 

 

 

GND

GND

H23

IN

 

 

 

 

 

 

D109#

D109#

H24

IN/OUT

 

 

 

 

 

 

GND

GND

H25

IN

 

 

 

 

 

 

GND

GND

J01

IN

 

 

 

 

 

 

VCTERM

VCTERM

J02

IN

 

 

 

 

 

 

D013#

D13#

J03

IN/OUT

 

 

 

 

 

 

GND

GND

J04

IN

 

 

 

 

 

 

DEP01#

DEP1#

J05

IN/OUT

 

 

 

 

 

 

VCTERM

VCTERM

J06

IN

 

 

 

 

 

 

DEP00#

DEP0#

J07

IN/OUT

 

 

 

 

 

 

GND

GND

J08

IN

 

 

 

 

 

 

DEP04#

DEP4#

J09

IN/OUT

 

 

 

 

 

 

VCTERM

VCTERM

J10

IN

 

 

 

 

 

 

DEP05#

DEP5#

J11

IN/OUT

 

 

 

 

 

 

GND

GND

J12

IN

 

 

 

 

 

 

D047#

D47#

J13

IN/OUT

 

 

 

 

 

 

VCTERM

VCTERM

J14

IN

 

 

 

 

 

 

D078#

D78#

J15

IN/OUT

 

 

 

 

 

 

Datasheet

57

Image 57
Contents Intel Itanium 2 Processor DatasheetDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures BINIT#, HIT#, HITM#, BNR#, TND#, BERR# Tables106 Revision No Description Date Revision HistoryIntel Itanium 2 Processor Product FeaturesDatasheet Processor Abstraction Layer OverviewMixing Processors of Different Frequencies and Cache Sizes TerminologyState of Data Title Document Number Reference DocumentsIntroduction System Bus Power Pins System Bus SignalsSignal Groups Itanium 2 Processor System BusSignal Descriptions Itanium 2 Processor System Bus Signal GroupsGroup Name Signals Package Specifications Itanium 2 Processor Package SpecificationsSymbol Parameter Core Minimum Typ Maximum Unit Itanium 2 Processor Power Supply Specifications Signal SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum UnitPower Good Signal DC Specifications AGTL+ Signals DC Specifications Sheet 2System Bus Clock Differential Hstl DC Specifications TAP Connection DC SpecificationsLvttl Signal DC Specifications SMBus DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum UnitMinimum Typ Maximum 11. SMBus AC Specifications12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1 Maximum Ratings12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2 Overshoot/Undershoot MagnitudeActivity Factor Overshoot/Undershoot Pulse DurationVcterm Reading Overshoot/Undershoot Specification TablesAbsolute Pulse Duration ns Parameter Description Specification UnitsOver AF = 1 Shoot0143 Wired-OR Signals 0513 22. Itanium 2 Processor Power Pod Connector Signals Power Pod Connector SignalsGroup Name Signals Power Pod Connector AbsoluteVID2 VID1 VID0 23. Processor Core Voltage Identification Code124. Processor Power States Itanium 2 Processor System Bus Clock and Processor ClockingState Transition Ramp Rate Comment Ratio of Bus Frequency A21# A20# A19# A18# A17# 25. Itanium 2 Processor System Bus RatiosSystem Bus Reset and Configuration Timings for Cold Reset 26. Connection for Unused Pins Sheet 1 Recommended Connections for Unused PinsPins/Pin Groups Recommended TAP SignalsSystem Management Signals 26. Connection for Unused Pins Sheet 2Lvttl Power Pod Signals Reserved PinsPinout Specifications Pin Name System Bus Input/Output Signal Name Pin/Signal Information Sorted by Pin Name Sheet 1Pin Name System Bus Input/Output Pin/Signal Information Sorted by Pin Name Sheet 2Pin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Location Pin/Signal Information Sorted by Pin Location Sheet 1Pin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Itanium 2 Processor Package Mechanical DimensionsSubstrate Units ProcessorItanium 2 Processor Package Power Tab Package Marking Processor Top-Side MarkingProcessor Bottom-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Alert Thermal FeaturesCase Temperature Specification Case TemperatureSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signal Descriptions System Management Interface SignalsSignal Name Pin Count Description System Management BusSystem Management Feature Specifications 9Xh SMBus Device AddressingProcessor Information ROM Eeprom SMBus Addressing on the Itanium 2 ProcessorProcessor Information ROM Format Sheet 1 Processor Information ROM Format Sheet 2 Offset Function Examples Section BitsCache Processor Information ROM Format Sheet 3 FeaturesOffset Function Examples Section Bits Package Part NumbersScratch Eeprom Processor Information ROM Format Sheet 4Other Current Address Read SMBus Packet Thermal Sensing DeviceRandom Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions Register Command Reset State Function 13. Command Byte Bit AssignmentThermal Sensing Device Registers Thermal Reference Registers15. Thermal Sensing Device Configuration Register Configuration RegisterThermal Limit Registers Status RegisterRegister Contents Conversion Rate Hz Conversion Rate Register16. Thermal Sensing Device Conversion Rate Register Alphabetical Signals Reference ATTR30# I/O Table A-2. Effective Memory Type Signal EncodingBCLKp/BCLKn 8 BE70# I/OTable A-3. Special Transaction Encoding on Byte Enables Special Transaction Byte Enables70#BERR# I/O 11 BNR# I/O BINIT# I/O12 BPM50# I/O BPRI#Bus Signal Agent 0 Pins Agent 3 Pins Table A-6. BR30# Signals and Agent IDsBREQ30# I/O Pin SampledD1270# I/O CCL# I/O# I/O DBSYC1# ODEFER# DBSYC2# O24 DEN# I/O 25 DEP150# I/ODRDY# I/O 27 DPS# I/ODRDYC1# O DRDYC2# OFERR# O 33 FCL# I/OHIT# I/O and HITM# I/O ID90#LEN20# I/O IP10#Table A-9. Length of Data Transfers LEN20#OWN# I/O LINT10PMI# REQ50# I/ORESET# 52 RP# I/OTransaction REQa50# REQb50# RSP# RS20#SBSYC1# O SBSYC2# OTDO O STBn70# and STBp70# I/OTHRMTRIP# O Table A-11. STBp70# and STBn70# AssociationsTable A-12. Output Signals Sheet 1 Signal SummariesName Active Level Clock Signal Group TND# I/OTable A-12. Output Signals Sheet 2 Table A-13. Input SignalsName Active Level Clock Signal Group Qualified Table A-15. Input/Output Signals Multiple Driver Table A-14. Input/Output Signals Single Driver108