Intel manual Itanium 2 Processor Package Specifications

Page 17

 

Electrical Specifications

VCTERM

System bus termination voltage.

GND

System ground.

N/C

No connection can be made to these pins.

TERMA, TERMB

The Itanium 2 processor uses two pins to control the on-die termination

 

function, TERMA and TERMB. Both of these termination pins must be

 

pulled to VCTERM in order to terminate the system bus using the on-die

 

termination resistors. Both of these termination pins must be pulled to

 

GND in order to use off-die termination.

TUNER1, TUNER2

TUNER1 is used to control the slew rate of the system bus I/O buffers.

 

The nominal value for the TUNER1 resistor is 150 ohms. A lower

 

resistance will cause a faster slew rate. TUNER2 is used to control the

 

termination resistance for the system bus I/O buffers. The nominal value

 

for the TUNER2 resistor is 150 ohms. A lower resistance will cause a

 

lower on-die termination resistance. On-die termination mode will only

 

be selected if the TERMA and TERMB pins are terminated as indicated

 

above.

VCCMON, VSSMON

These pins provide a remote sense connection from the processor to the

 

power pod. No connections that constitute a current load can be made to

 

these pins.

2.3Package Specifications

Table 2-2through Table 2-9list the DC voltage, current and power specifications for the Itanium 2 processor. The voltage and current specifications are defined at the Itanium 2 processor pins. Operational specifications listed in Table 2-2through Table 2-9are only valid while meeting specifications for case temperature, clock frequency, and input voltages.

Table 2-2. Itanium® 2 Processor Package Specifications

Symbol

Parameter

Core

Minimum

Typ

Maximum

Unit

Notes

Frequency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCTERM

Termination Voltage

All

1.2 –1.5%

1.2

1.2 +1.5%

V

1

 

RTERM

Recommended Termination

All

 

45

 

W

2

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VTAP

Test Access Port Voltage

All

1.2 –1.5%

1.2

1.5

V

 

 

(VCCTAP)

 

 

 

 

 

 

ICTERM

Termination Voltage Current

All

 

 

7.2

A

3

 

 

 

PWRMAX

Maximum Processor Power

All

 

 

130

W

4

 

 

 

PWRTDE

Thermal Design Envelope

All

 

 

130

W

5

 

 

 

PWRTDP

Thermal Design Power

900 MHz

 

 

90

W

6

 

 

 

 

 

1.0 GHz

 

 

100

W

6

 

 

 

 

 

 

 

 

 

 

1.3 GHz

 

 

97

W

6

 

 

 

 

 

 

 

 

 

 

1.4 GHz

 

 

91

W

6

 

 

 

 

 

 

 

 

 

 

1.5 GHz

 

 

107

W

6

 

 

 

 

 

 

 

 

 

 

1.6 GHz

 

 

122

W

6

 

 

 

 

 

 

 

 

 

 

1.66 GHz

 

 

122

W

6

 

 

 

 

 

 

 

 

Datasheet

17

Image 17
Contents Intel Itanium 2 Processor DatasheetDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures BINIT#, HIT#, HITM#, BNR#, TND#, BERR# Tables106 Revision No Description Date Revision HistoryIntel Itanium 2 Processor Product FeaturesDatasheet Processor Abstraction Layer OverviewState of Data Mixing Processors of Different Frequencies and Cache SizesTerminology Title Document Number Reference DocumentsIntroduction System Bus Power Pins System Bus SignalsSignal Groups Itanium 2 Processor System BusGroup Name Signals Signal DescriptionsItanium 2 Processor System Bus Signal Groups Symbol Parameter Core Minimum Typ Maximum Unit Package SpecificationsItanium 2 Processor Package Specifications Itanium 2 Processor Power Supply Specifications Signal SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum UnitPower Good Signal DC Specifications AGTL+ Signals DC Specifications Sheet 2System Bus Clock Differential Hstl DC Specifications TAP Connection DC SpecificationsLvttl Signal DC Specifications SMBus DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum UnitMinimum Typ Maximum 11. SMBus AC Specifications12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1 Maximum Ratings12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2 Overshoot/Undershoot MagnitudeActivity Factor Overshoot/Undershoot Pulse DurationVcterm Reading Overshoot/Undershoot Specification TablesAbsolute Pulse Duration ns Parameter Description Specification UnitsOver AF = 1 Shoot0143 Wired-OR Signals 0513 22. Itanium 2 Processor Power Pod Connector Signals Power Pod Connector SignalsGroup Name Signals Power Pod Connector AbsoluteVID2 VID1 VID0 23. Processor Core Voltage Identification Code1State Transition Ramp Rate Comment 24. Processor Power StatesItanium 2 Processor System Bus Clock and Processor Clocking Ratio of Bus Frequency A21# A20# A19# A18# A17# 25. Itanium 2 Processor System Bus RatiosSystem Bus Reset and Configuration Timings for Cold Reset 26. Connection for Unused Pins Sheet 1 Recommended Connections for Unused PinsPins/Pin Groups Recommended TAP SignalsSystem Management Signals 26. Connection for Unused Pins Sheet 2Lvttl Power Pod Signals Reserved PinsPinout Specifications Pin Name System Bus Input/Output Signal Name Pin/Signal Information Sorted by Pin Name Sheet 1Pin Name System Bus Input/Output Pin/Signal Information Sorted by Pin Name Sheet 2Pin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Location Pin/Signal Information Sorted by Pin Location Sheet 1Pin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Itanium 2 Processor Package Mechanical DimensionsSubstrate Units ProcessorItanium 2 Processor Package Power Tab Processor Bottom-Side Marking Package MarkingProcessor Top-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Alert Thermal FeaturesCase Temperature Specification Case TemperatureSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signal Descriptions System Management Interface SignalsSignal Name Pin Count Description System Management BusSystem Management Feature Specifications 9Xh SMBus Device AddressingProcessor Information ROM Format Sheet 1 Processor Information ROMEeprom SMBus Addressing on the Itanium 2 Processor Cache Processor Information ROM Format Sheet 2Offset Function Examples Section Bits Processor Information ROM Format Sheet 3 FeaturesOffset Function Examples Section Bits Package Part NumbersOther Scratch EepromProcessor Information ROM Format Sheet 4 Current Address Read SMBus Packet Thermal Sensing DeviceRandom Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions Register Command Reset State Function 13. Command Byte Bit AssignmentThermal Sensing Device Registers Thermal Reference Registers15. Thermal Sensing Device Configuration Register Configuration RegisterThermal Limit Registers Status Register16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate HzConversion Rate Register Alphabetical Signals Reference ATTR30# I/O Table A-2. Effective Memory Type Signal EncodingBCLKp/BCLKn 8 BE70# I/OBERR# I/O Table A-3. Special Transaction Encoding on Byte EnablesSpecial Transaction Byte Enables70# 11 BNR# I/O BINIT# I/O12 BPM50# I/O BPRI#Bus Signal Agent 0 Pins Agent 3 Pins Table A-6. BR30# Signals and Agent IDsBREQ30# I/O Pin SampledD1270# I/O CCL# I/O# I/O DBSYC1# ODEFER# DBSYC2# O24 DEN# I/O 25 DEP150# I/ODRDY# I/O 27 DPS# I/ODRDYC1# O DRDYC2# OFERR# O 33 FCL# I/OHIT# I/O and HITM# I/O ID90#LEN20# I/O IP10#Table A-9. Length of Data Transfers LEN20#OWN# I/O LINT10PMI# REQ50# I/OTransaction REQa50# REQb50# RESET#52 RP# I/O RSP# RS20#SBSYC1# O SBSYC2# OTDO O STBn70# and STBp70# I/OTHRMTRIP# O Table A-11. STBp70# and STBn70# AssociationsTable A-12. Output Signals Sheet 1 Signal SummariesName Active Level Clock Signal Group TND# I/OName Active Level Clock Signal Group Qualified Table A-12. Output Signals Sheet 2Table A-13. Input Signals Table A-15. Input/Output Signals Multiple Driver Table A-14. Input/Output Signals Single Driver108