Intel manual Intel Itanium 2 Processor, Product Features

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Intel® Itanium® 2 Processor

Intel® Itanium® 2 Processor 1.66 GHz with 9 MB L3 Cache Intel® Itanium® 2 Processor 1.66 GHz with 6 MB L3 Cache Intel® Itanium® 2 Processor 1.6 GHz with 9 MB L3 Cache Intel® Itanium® 2 Processor 1.6 GHz with 6 MB L3 Cache Intel® Itanium® 2 Processor 1.5 GHz with 6 MB L3 Cache Intel® Itanium® 2 Processor 1.5 GHz with 4 MB L3 Cache Intel® Itanium® 2 Processor 1.4 GHz with 4 MB L3 Cache Intel® Itanium® 2 Processor 1.3 GHz with 3 MB L3 Cache Intel® Itanium® 2 Processor 1.0 GHz with 3 MB L3 Cache Intel® Itanium® 2 Processor 900 MHz with 1.5 MB L3 Cache

Product Features

Wide, parallel hardware based on Intel® Itanium® architecture for high performance:

Integrated on-die cache of up to 9 MB; cache hints for L1, L2, and L3 caches for reduced memory latency.

128 general and 128 floating-point registers supporting register rotation.

Register stack engine for effective management of processor resources.

Support for predication and speculation.

Extensive RAS features for business-critical applications:

Full SMBus compatibility.

Enhanced machine check architecture with extensive ECC and parity protection.

Enhanced thermal management.

Built-in processor information ROM (PIROM).

Built-in programmable EEPROM.

High bandwidth system bus for multiprocessor scalability:

Up to 10.6 GB/s bandwidth.

128-bit wide data bus.

50-bits of physical memory addressing and 64- bits of virtual addressing.

Up to four processors on the same system bus at 400 MHz data bus frequency.

Up to two processors on the same system bus at 533 MHz or 667 MHz data bus frequency.

Expandable to systems with multiple system buses.

Features to support flexible platform environments:

Support for IA-32 application binaries.

Bi-endian support.

Processor abstraction layer eliminates processor dependencies.

The Intel® Itanium® 2 processor is designed to address the needs of high-performance servers and workstations. The Itanium architecture goes beyond RISC and CISC approaches by employing Explicitly Parallel Instruction Computing (EPIC), which pairs extensive processing resources with intelligent compilers that enable parallel execution explicit to the processor. The processor’s large internal resources combine with predication and speculation to enable optimization for high performance applications running on multiple operating systems, including versions of Microsoft Windows*, HP-UX* and Linux*. The Itanium 2 processor is designed to support very large scale systems, including those employing thousands of processors, to provide the processing power and performance head room for the most demanding enterprise and technical computing applications. SMBus compatibility and comprehensive reliability, availability and serviceability (RAS) features make the Itanium 2 processor ideal for applications requiring high up-time. For high performance servers and workstations, the Itanium 2 processor offers outstanding performance and reliability for today’s applications and the scalability to address the growing e-business needs of tomorrow.

Datasheet

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Contents Intel Itanium 2 Processor DatasheetDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures BINIT#, HIT#, HITM#, BNR#, TND#, BERR# Tables106 Revision No Description Date Revision HistoryIntel Itanium 2 Processor Product FeaturesDatasheet Processor Abstraction Layer OverviewMixing Processors of Different Frequencies and Cache Sizes TerminologyState of Data Title Document Number Reference DocumentsIntroduction System Bus Power Pins System Bus SignalsSignal Groups Itanium 2 Processor System BusSignal Descriptions Itanium 2 Processor System Bus Signal GroupsGroup Name Signals Package Specifications Itanium 2 Processor Package SpecificationsSymbol Parameter Core Minimum Typ Maximum Unit Itanium 2 Processor Power Supply Specifications Signal SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum UnitPower Good Signal DC Specifications AGTL+ Signals DC Specifications Sheet 2System Bus Clock Differential Hstl DC Specifications TAP Connection DC SpecificationsLvttl Signal DC Specifications SMBus DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum UnitMinimum Typ Maximum 11. SMBus AC Specifications12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1 Maximum Ratings12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2 Overshoot/Undershoot MagnitudeActivity Factor Overshoot/Undershoot Pulse DurationVcterm Reading Overshoot/Undershoot Specification TablesAbsolute Pulse Duration ns Parameter Description Specification UnitsOver AF = 1 Shoot0143 Wired-OR Signals 0513 22. Itanium 2 Processor Power Pod Connector Signals Power Pod Connector SignalsGroup Name Signals Power Pod Connector AbsoluteVID2 VID1 VID0 23. Processor Core Voltage Identification Code124. Processor Power States Itanium 2 Processor System Bus Clock and Processor ClockingState Transition Ramp Rate Comment Ratio of Bus Frequency A21# A20# A19# A18# A17# 25. Itanium 2 Processor System Bus RatiosSystem Bus Reset and Configuration Timings for Cold Reset 26. Connection for Unused Pins Sheet 1 Recommended Connections for Unused PinsPins/Pin Groups Recommended TAP SignalsSystem Management Signals 26. Connection for Unused Pins Sheet 2Lvttl Power Pod Signals Reserved PinsPinout Specifications Pin Name System Bus Input/Output Signal Name Pin/Signal Information Sorted by Pin Name Sheet 1Pin Name System Bus Input/Output Pin/Signal Information Sorted by Pin Name Sheet 2Pin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Location Pin/Signal Information Sorted by Pin Location Sheet 1Pin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Itanium 2 Processor Package Mechanical DimensionsSubstrate Units ProcessorItanium 2 Processor Package Power Tab Package Marking Processor Top-Side MarkingProcessor Bottom-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Alert Thermal FeaturesCase Temperature Specification Case TemperatureSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signal Descriptions System Management Interface SignalsSignal Name Pin Count Description System Management BusSystem Management Feature Specifications 9Xh SMBus Device AddressingProcessor Information ROM Eeprom SMBus Addressing on the Itanium 2 ProcessorProcessor Information ROM Format Sheet 1 Processor Information ROM Format Sheet 2 Offset Function Examples Section BitsCache Processor Information ROM Format Sheet 3 FeaturesOffset Function Examples Section Bits Package Part NumbersScratch Eeprom Processor Information ROM Format Sheet 4Other Current Address Read SMBus Packet Thermal Sensing DeviceRandom Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions Register Command Reset State Function 13. Command Byte Bit AssignmentThermal Sensing Device Registers Thermal Reference Registers15. Thermal Sensing Device Configuration Register Configuration RegisterThermal Limit Registers Status RegisterRegister Contents Conversion Rate Hz Conversion Rate Register16. Thermal Sensing Device Conversion Rate Register Alphabetical Signals Reference ATTR30# I/O Table A-2. Effective Memory Type Signal EncodingBCLKp/BCLKn 8 BE70# I/OTable A-3. Special Transaction Encoding on Byte Enables Special Transaction Byte Enables70#BERR# I/O 11 BNR# I/O BINIT# I/O12 BPM50# I/O BPRI#Bus Signal Agent 0 Pins Agent 3 Pins Table A-6. BR30# Signals and Agent IDsBREQ30# I/O Pin SampledD1270# I/O CCL# I/O# I/O DBSYC1# ODEFER# DBSYC2# O24 DEN# I/O 25 DEP150# I/ODRDY# I/O 27 DPS# I/ODRDYC1# O DRDYC2# OFERR# O 33 FCL# I/OHIT# I/O and HITM# I/O ID90#LEN20# I/O IP10#Table A-9. Length of Data Transfers LEN20#OWN# I/O LINT10PMI# REQ50# I/ORESET# 52 RP# I/OTransaction REQa50# REQb50# RSP# RS20#SBSYC1# O SBSYC2# OTDO O STBn70# and STBp70# I/OTHRMTRIP# O Table A-11. STBp70# and STBn70# AssociationsTable A-12. Output Signals Sheet 1 Signal SummariesName Active Level Clock Signal Group TND# I/OTable A-12. Output Signals Sheet 2 Table A-13. Input SignalsName Active Level Clock Signal Group Qualified Table A-15. Input/Output Signals Multiple Driver Table A-14. Input/Output Signals Single Driver108