Intel Itanium 2 Processor manual Pin/Signal Information Sorted by Pin Name Sheet 1

Page 38

Pinout Specifications

Table 3-1provides the Itanium 2 processor pin list in alphabetical order.

Table 3-2provides the Itanium 2 processor pin list by pin location.

Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 1 of 15)

Pin Name

System Bus

Pin

Input/Output

Notes

Signal Name

Location

 

 

 

 

 

 

 

 

3.3V

 

B02

IN

SMBus supply voltage

 

 

 

 

 

A003#

AA03#/EXF0#

V06

IN/OUT

 

 

 

 

 

 

A004#

AA04#/EXF1#

V02

IN/OUT

 

 

 

 

 

 

A005#

AA05#/EXF2#

U03

IN/OUT

 

 

 

 

 

 

A006#

AA06#/EXF3#

W03

IN/OUT

 

 

 

 

 

 

A007#

AA07#/EXF4#

Y02

IN/OUT

 

 

 

 

 

 

A008#

AA08#/BE0#

Y06

IN/OUT

 

 

 

 

 

 

A009#

AA09#/BE1#

U07

IN/OUT

 

 

 

 

 

 

A010#

AA10#/BE2#

V04

IN/OUT

 

 

 

 

 

 

A011#

AA11#/BE3#

AA05

IN/OUT

 

 

 

 

 

 

A012#

AA12#/BE4#

W05

IN/OUT

 

 

 

 

 

 

A013#

AA13#/BE5#

Y04

IN/OUT

 

 

 

 

 

 

A014#

AA14#/BE6#

W07

IN/OUT

 

 

 

 

 

 

A015#

AA15#/BE7#

V08

IN/OUT

 

 

 

 

 

 

A016#

AA16#/DID0#

U13

IN/OUT

 

 

 

 

 

 

A017#

AA17#/DID1#

Y08

IN/OUT

 

 

 

 

 

 

A018#

AA18#/DID2#

U09

IN/OUT

 

 

 

 

 

 

A019#

AA19#/DID3#

V12

IN/OUT

 

 

 

 

 

 

A020#

AA20#/DID4#

V10

IN/OUT

 

 

 

 

 

 

A021#

AA21#/DID5#

W09

IN/OUT

 

 

 

 

 

 

A022#

AA22#/DID6#

W13

IN/OUT

 

 

 

 

 

 

A023#

AA23#/DID7#

AA11

IN/OUT

 

 

 

 

 

 

A024#

AA24#/DID8#

Y10

IN/OUT

 

 

 

 

 

 

A025#

AA25#/DID9#

Y12

IN/OUT

 

 

 

 

 

 

A026#

AA26#/AB26#

W11

IN/OUT

 

 

 

 

 

 

A027#

AA27#/xTPRValue0#

U19

IN/OUT

 

 

 

 

 

 

A028#

AA28#/xTPRValue1#

U15

IN/OUT

 

 

 

 

 

 

A029#

AA29#/xTPRValue2#

V18

IN/OUT

 

 

 

 

 

 

A030#

AA30#/xTPRValue3#

W19

IN/OUT

 

 

 

 

 

 

A031#

AA31#/xTPRDisable#

V14

IN/OUT

 

 

 

 

 

 

A032#

AA32#/ATTR0#

W17

IN/OUT

 

 

 

 

 

 

A033#

AA33#/ATTR1#

AA17

IN/OUT

 

 

 

 

 

 

A034#

AA34#/ATTR2#

Y14

IN/OUT

 

 

 

 

 

 

A035#

AA35#/ATTR3#

Y18

IN/OUT

 

 

 

 

 

 

A036#

AA36#/AB36#

Y16

IN/OUT

 

 

 

 

 

 

A037#

AA37#/AB37#

W15

IN/OUT

 

 

 

 

 

 

A038#

AA38#/AB38#

V16

IN/OUT

 

 

 

 

 

 

A039#

AA39#/AB39#

Y20

IN/OUT

 

 

 

 

 

 

38

Datasheet

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Image 38
Page 37 Page 39
Contents Datasheet Intel Itanium 2 ProcessorDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR#106 Revision History Revision No Description DateProduct Features Intel Itanium 2 ProcessorDatasheet Overview Processor Abstraction LayerState of Data Mixing Processors of Different Frequencies and Cache SizesTerminology Reference Documents Title Document NumberIntroduction Signal Groups System Bus SignalsSystem Bus Power Pins Itanium 2 Processor System BusGroup Name Signals Signal DescriptionsItanium 2 Processor System Bus Signal Groups Symbol Parameter Core Minimum Typ Maximum Unit Package SpecificationsItanium 2 Processor Package Specifications AGTL+ Signals DC Specifications Sheet 1 Signal SpecificationsItanium 2 Processor Power Supply Specifications Symbol Parameter Minimum Typ Maximum UnitSystem Bus Clock Differential Hstl DC Specifications AGTL+ Signals DC Specifications Sheet 2Power Good Signal DC Specifications TAP Connection DC SpecificationsSystem Symbol Parameter SMBus DC SpecificationsLvttl Signal DC Specifications Minimum Typ Maximum Unit11. SMBus AC Specifications Minimum Typ MaximumMaximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2Overshoot/Undershoot Pulse Duration Activity FactorReading Overshoot/Undershoot Specification Tables VctermOver Parameter Description Specification UnitsAbsolute Pulse Duration ns AF = 1 Shoot0143 Wired-OR Signals 0513 Group Name Signals Power Pod Connector Power Pod Connector Signals22. Itanium 2 Processor Power Pod Connector Signals Absolute23. Processor Core Voltage Identification Code1 VID2 VID1 VID0State Transition Ramp Rate Comment 24. Processor Power StatesItanium 2 Processor System Bus Clock and Processor Clocking 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17#System Bus Reset and Configuration Timings for Cold Reset Pins/Pin Groups Recommended Recommended Connections for Unused Pins26. Connection for Unused Pins Sheet 1 TAP SignalsLvttl Power Pod Signals 26. Connection for Unused Pins Sheet 2System Management Signals Reserved PinsPinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal NamePin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/OutputPin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 LocationPin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor PackageProcessor Substrate UnitsItanium 2 Processor Package Power Tab Processor Bottom-Side Marking Package MarkingProcessor Top-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal AlertSymbol Parameter Core Minimum Maximum Unit Case TemperatureCase Temperature Specification Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications Signal Name Pin Count Description System Management Interface SignalsSystem Management Interface Signal Descriptions System Management BusSystem Management Feature Specifications SMBus Device Addressing 9XhProcessor Information ROM Format Sheet 1 Processor Information ROMEeprom SMBus Addressing on the Itanium 2 Processor Cache Processor Information ROM Format Sheet 2Offset Function Examples Section Bits Offset Function Examples Section Bits Package FeaturesProcessor Information ROM Format Sheet 3 Part NumbersOther Scratch EepromProcessor Information ROM Format Sheet 4 Random Address Read SMBus Packet Thermal Sensing DeviceCurrent Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions Thermal Sensing Device Registers 13. Command Byte Bit AssignmentRegister Command Reset State Function Thermal Reference RegistersThermal Limit Registers Configuration Register15. Thermal Sensing Device Configuration Register Status Register16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate HzConversion Rate Register Alphabetical Signals Reference BCLKp/BCLKn Table A-2. Effective Memory Type Signal EncodingATTR30# I/O 8 BE70# I/OBERR# I/O Table A-3. Special Transaction Encoding on Byte EnablesSpecial Transaction Byte Enables70# 12 BPM50# I/O BINIT# I/O11 BNR# I/O BPRI#BREQ30# I/O Table A-6. BR30# Signals and Agent IDsBus Signal Agent 0 Pins Agent 3 Pins Pin Sampled# I/O CCL# I/OD1270# I/O DBSYC1# O24 DEN# I/O DBSYC2# ODEFER# 25 DEP150# I/ODRDYC1# O 27 DPS# I/ODRDY# I/O DRDYC2# OHIT# I/O and HITM# I/O 33 FCL# I/OFERR# O ID90#Table A-9. Length of Data Transfers IP10#LEN20# I/O LEN20#PMI# LINT10OWN# I/O REQ50# I/OTransaction REQa50# REQb50# RESET#52 RP# I/O SBSYC1# O RS20#RSP# SBSYC2# OTHRMTRIP# O STBn70# and STBp70# I/OTDO O Table A-11. STBp70# and STBn70# AssociationsName Active Level Clock Signal Group Signal SummariesTable A-12. Output Signals Sheet 1 TND# I/OName Active Level Clock Signal Group Qualified Table A-12. Output Signals Sheet 2Table A-13. Input Signals Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver108
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