Intel Itanium 2 Processor manual Pin/Signal Information Sorted by Pin Name Sheet 15

Page 52

Pinout Specifications

Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 15 of 15)

Pin Name

System Bus

Pin

Input/Output

Notes

Signal Name

Location

 

 

 

 

 

 

 

 

VCTERM

VCTERM

G04

IN

 

 

 

 

 

 

VCTERM

VCTERM

G08

IN

 

 

 

 

 

 

VCTERM

VCTERM

G12

IN

 

 

 

 

 

 

VCTERM

VCTERM

G16

IN

 

 

 

 

 

 

VCTERM

VCTERM

G20

IN

 

 

 

 

 

 

VCTERM

VCTERM

G24

IN

 

 

 

 

 

 

VCTERM

VCTERM

J02

IN

 

 

 

 

 

 

VCTERM

VCTERM

J06

IN

 

 

 

 

 

 

VCTERM

VCTERM

J10

IN

 

 

 

 

 

 

VCTERM

VCTERM

J14

IN

 

 

 

 

 

 

VCTERM

VCTERM

J18

IN

 

 

 

 

 

 

VCTERM

VCTERM

J22

IN

 

 

 

 

 

 

VCTERM

VCTERM

L01

IN

 

 

 

 

 

 

VCTERM

VCTERM

L04

IN

 

 

 

 

 

 

VCTERM

VCTERM

L08

IN

 

 

 

 

 

 

VCTERM

VCTERM

L12

IN

 

 

 

 

 

 

VCTERM

VCTERM

L16

IN

 

 

 

 

 

 

VCTERM

VCTERM

L20

IN

 

 

 

 

 

 

VCTERM

VCTERM

L24

IN

 

 

 

 

 

 

VCTERM

VCTERM

N02

IN

 

 

 

 

 

 

VCTERM

VCTERM

N06

IN

 

 

 

 

 

 

VCTERM

VCTERM

N10

IN

 

 

 

 

 

 

VCTERM

VCTERM

N14

IN

 

 

 

 

 

 

VCTERM

VCTERM

N18

IN

 

 

 

 

 

 

VCTERM

VCTERM

N22

IN

 

 

 

 

 

 

VCTERM

VCTERM

R01

IN

 

 

 

 

 

 

VCTERM

VCTERM

R04

IN

 

 

 

 

 

 

VCTERM

VCTERM

R08

IN

 

 

 

 

 

 

VCTERM

VCTERM

R12

IN

 

 

 

 

 

 

VCTERM

VCTERM

R16

IN

 

 

 

 

 

 

VCTERM

VCTERM

R20

IN

 

 

 

 

 

 

VCTERM

VCTERM

R24

IN

 

 

 

 

 

 

VCTERM

VCTERM

U02

IN

 

 

 

 

 

 

VCTERM

VCTERM

U06

IN

 

 

 

 

 

 

VCTERM

VCTERM

U10

IN

 

 

 

 

 

 

VCTERM

VCTERM

U14

IN

 

 

 

 

 

 

VCTERM

VCTERM

U18

IN

 

 

 

 

 

 

VCTERM

VCTERM

U22

IN

 

 

 

 

 

 

VCTERM

VCTERM

U25

IN

 

 

 

 

 

 

VSSMON

VSSMON

A09

OUT

Power pod signal

 

 

 

 

 

52

Datasheet

Image 52
Contents Datasheet Intel Itanium 2 ProcessorDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR#106 Revision History Revision No Description DateProduct Features Intel Itanium 2 ProcessorDatasheet Overview Processor Abstraction LayerTerminology Mixing Processors of Different Frequencies and Cache SizesState of Data Reference Documents Title Document NumberIntroduction System Bus Signals System Bus Power PinsSignal Groups Itanium 2 Processor System BusItanium 2 Processor System Bus Signal Groups Signal DescriptionsGroup Name Signals Itanium 2 Processor Package Specifications Package SpecificationsSymbol Parameter Core Minimum Typ Maximum Unit Signal Specifications Itanium 2 Processor Power Supply SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum UnitAGTL+ Signals DC Specifications Sheet 2 Power Good Signal DC SpecificationsSystem Bus Clock Differential Hstl DC Specifications TAP Connection DC SpecificationsSMBus DC Specifications Lvttl Signal DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum Unit11. SMBus AC Specifications Minimum Typ MaximumMaximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2Overshoot/Undershoot Pulse Duration Activity FactorReading Overshoot/Undershoot Specification Tables VctermParameter Description Specification Units Absolute Pulse Duration nsOver AF = 1 Shoot0143 Wired-OR Signals 0513 Power Pod Connector Signals 22. Itanium 2 Processor Power Pod Connector SignalsGroup Name Signals Power Pod Connector Absolute23. Processor Core Voltage Identification Code1 VID2 VID1 VID0Itanium 2 Processor System Bus Clock and Processor Clocking 24. Processor Power StatesState Transition Ramp Rate Comment 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17#System Bus Reset and Configuration Timings for Cold Reset Recommended Connections for Unused Pins 26. Connection for Unused Pins Sheet 1Pins/Pin Groups Recommended TAP Signals26. Connection for Unused Pins Sheet 2 System Management SignalsLvttl Power Pod Signals Reserved PinsPinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal NamePin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/OutputPin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 LocationPin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor PackageProcessor Substrate UnitsItanium 2 Processor Package Power Tab Processor Top-Side Marking Package MarkingProcessor Bottom-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal AlertCase Temperature Case Temperature SpecificationSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signals System Management Interface Signal DescriptionsSignal Name Pin Count Description System Management BusSystem Management Feature Specifications SMBus Device Addressing 9XhEeprom SMBus Addressing on the Itanium 2 Processor Processor Information ROMProcessor Information ROM Format Sheet 1 Offset Function Examples Section Bits Processor Information ROM Format Sheet 2Cache Features Processor Information ROM Format Sheet 3Offset Function Examples Section Bits Package Part NumbersProcessor Information ROM Format Sheet 4 Scratch EepromOther Thermal Sensing Device Current Address Read SMBus PacketRandom Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions 13. Command Byte Bit Assignment Register Command Reset State FunctionThermal Sensing Device Registers Thermal Reference RegistersConfiguration Register 15. Thermal Sensing Device Configuration RegisterThermal Limit Registers Status RegisterConversion Rate Register Register Contents Conversion Rate Hz16. Thermal Sensing Device Conversion Rate Register Alphabetical Signals Reference Table A-2. Effective Memory Type Signal Encoding ATTR30# I/OBCLKp/BCLKn 8 BE70# I/OSpecial Transaction Byte Enables70# Table A-3. Special Transaction Encoding on Byte EnablesBERR# I/O BINIT# I/O 11 BNR# I/O12 BPM50# I/O BPRI#Table A-6. BR30# Signals and Agent IDs Bus Signal Agent 0 Pins Agent 3 PinsBREQ30# I/O Pin SampledCCL# I/O D1270# I/O# I/O DBSYC1# ODBSYC2# O DEFER#24 DEN# I/O 25 DEP150# I/O27 DPS# I/O DRDY# I/ODRDYC1# O DRDYC2# O33 FCL# I/O FERR# OHIT# I/O and HITM# I/O ID90#IP10# LEN20# I/OTable A-9. Length of Data Transfers LEN20#LINT10 OWN# I/OPMI# REQ50# I/O52 RP# I/O RESET#Transaction REQa50# REQb50# RS20# RSP#SBSYC1# O SBSYC2# OSTBn70# and STBp70# I/O TDO OTHRMTRIP# O Table A-11. STBp70# and STBn70# AssociationsSignal Summaries Table A-12. Output Signals Sheet 1Name Active Level Clock Signal Group TND# I/OTable A-13. Input Signals Table A-12. Output Signals Sheet 2Name Active Level Clock Signal Group Qualified Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver108