Intel Itanium 2 Processor manual SMBus DC Specifications, Lvttl Signal DC Specifications

Electrical Specifications

Table 2-8. SMBus DC Specifications

Symbol	Parameter	Minimum	Typ	Maximum	Unit	Notes
3.3V	VCC for the System Management	3.14	3.3	3.47	V	3.3V ±5%
	Components
VIL	Input Low Voltage	–0.3		0.3*3.3V	V
VIH	Input High Voltage	2.31		3.47	V	Max =
						3.3 +5%
						Min +
						0.7*3.3V
VOL	Output Low Voltage			0.4	V
I3.3V	3.3V Supply Current		5.0	30.0	mA
IOL	Output Low Current			3	mA	1
IOL2	Output Low Current	6			mA	2
ILI	Input Leakage Current			10	µA
ILO	Output Leakage Current			10	µA
NOTES:

1.The value specified for IOL applies to all signals except for THRMALERT#.

2.The value specified for IOL2 applies only to THRMALERT# which is an open drain signal.

Table 2-9. LVTTL Signal DC Specifications

Symbol	Parameter	Minimum	Maximum	Unit	Notes
VIL	Input Low Voltage		0.8	V
VIH	Input High Voltage	2.0	3.63	V
VOL	Output Low Voltage		0.4	V
VOH	Output High Voltage	2.4		V

Table 2-10through Table 2-11list the AC specifications for the Itanium 2 processor’s clock and SMBus (timing diagrams begin with Figure 2-1). The Itanium 2 processor uses a differential HSTL clocking scheme with a frequency of 200, 266 or 333 MHz. The SMBus is a subset of the I2C* interface which supports operation of up to 100 kHz.

Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 1 of 2)

		System
Symbol	Parameter	Bus	Minimum	Typ	Maximum	Unit	Figure	Notes
		Clock
		(MHz)
Tperiod	BCLKp Period	200		5.0		ns	Figure 2-1
Tskew	System Clock Skew	200		100		ps		1
fBCLK	BCLKp Frequency	200	200		200	MHz	Figure 2-1	2
Tjitter	BCLKp Input Jitter	200			100	ps	Figure 2-1	3
Thigh	BCLKp High Time	200	2.25	2.5	2.75	ns	Figure 2-1	4
Tlow	BCLKp Low Time	200	2.25	2.5	2.75	ns	Figure 2-1	4
Tperiod	BCLKp Period	266		3.75		ns	Figure 2-1
Tskew	System Clock Skew	266			60	ps		5
fBCLK	BCLKp Frequency	266	266		266	MHz	Figure 2-1	2
Tjitter	BCLKp Input Jitter	266			50	ps	Figure 2-1	3
Thigh	BCLKp High Time	266	1.69	1.88	2.06	ns	Figure 2-1	4

20 Datasheet