Intel Itanium 2 Processor Thermal Sensing Device, Current Address Read SMBus Packet, Device Data

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System Management Feature Specifications

controller continues to transmit data bytes until it terminates the sequence with a stop. All data bytes will result in an acknowledge from the Scratch EEPROM. If more than eight bytes are written, the internal address will “roll over” and the previous data will be overwritten.

In Table 6-5through Table 6-7, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read, ‘W’ represents a write bit, ‘A’ represents an acknowledge, and ‘///’ represents a negative acknowledge. The shaded bits are transmitted by the processor information ROM or Scratch EEPROM and the bits that are not shaded are transmitted by the SMBus host controller. In the tables the data addresses indicate eight bits. The SMBus host controller should transmit eight bits, but as there are only 128 addresses, the most significant bit is a don’t care.

Table 6-5. Current Address Read SMBus Packet

S

Device

R

A

Data

///

P

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

1

7 bits

1

1

8 bits

1

1

 

 

 

 

 

 

 

Table 6-6. Random Address Read SMBus Packet

S

Device

W

A

Data

A

S

Device

R

A

Data

///

P

Address

Address

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

7 bits

1

1

8 bits

1

1

7 bits

1

1

8 bits

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6-7. Byte Write SMBus Packet

S

Device

W

A

Data

A

Data

A

P

Address

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

7 bits

0

1

8 bits

1

8 bits

1

1

 

 

 

 

 

 

 

 

 

6.5Thermal Sensing Device

The Itanium 2 processor’s thermal sensing device provides a means of acquiring thermal data from the processor. The accuracy of the thermal reading is expected to be better than ±3 °C. The thermal sensing device is composed of control logic, SMBus interface logic, a precision analog to digital converter, and a precision current source. The thermal sensing device drives a small current through a thermal diode located on the processor core and measures the voltage generated across the thermal diode by the current. With this information, the thermal sensing device computes a byte of temperature data. Software running on the processor or on a micro-controller can use the temperature data from the thermal sensing device to thermally manage the system.

The thermal sensing device provides a register with a data byte (seven bits plus sign) which contains a value corresponding to the sampled output of the thermal diode in the Itanium 2 processor core. The value of the byte read from the thermal sensor gives an accurate reading of processor core temperature at the time of the reading. This data can be used in conjunction with the upper temperature reference byte (provided in the processor information ROM) for thermal management purposes. The temperature data from the thermal sensor can be read out digitally using an SMBus read command (see Section 6.6). The thermal sensor detects when SMBus power is applied to the processor, and resets itself at power up.

The thermal sensing device also contains alarm registers to store thermal reference threshold data. These values can be individually programmed on the thermal sensor. If the measured temperature equals or exceeds the alarm threshold value, the appropriate bit is set in the thermal sensing device status register, which is also brought out to the Itanium 2 processor system bus via the

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Datasheet

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Contents Datasheet Intel Itanium 2 ProcessorDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR#106 Revision History Revision No Description DateProduct Features Intel Itanium 2 ProcessorDatasheet Overview Processor Abstraction LayerState of Data Mixing Processors of Different Frequencies and Cache SizesTerminology Reference Documents Title Document NumberIntroduction Signal Groups System Bus SignalsSystem Bus Power Pins Itanium 2 Processor System BusGroup Name Signals Signal DescriptionsItanium 2 Processor System Bus Signal Groups Symbol Parameter Core Minimum Typ Maximum Unit Package SpecificationsItanium 2 Processor Package Specifications AGTL+ Signals DC Specifications Sheet 1 Signal SpecificationsItanium 2 Processor Power Supply Specifications Symbol Parameter Minimum Typ Maximum UnitSystem Bus Clock Differential Hstl DC Specifications AGTL+ Signals DC Specifications Sheet 2Power Good Signal DC Specifications TAP Connection DC SpecificationsSystem Symbol Parameter SMBus DC SpecificationsLvttl Signal DC Specifications Minimum Typ Maximum Unit11. SMBus AC Specifications Minimum Typ MaximumMaximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2Overshoot/Undershoot Pulse Duration Activity FactorReading Overshoot/Undershoot Specification Tables VctermOver Parameter Description Specification UnitsAbsolute Pulse Duration ns AF = 1 Shoot0143 Wired-OR Signals 0513 Group Name Signals Power Pod Connector Power Pod Connector Signals22. Itanium 2 Processor Power Pod Connector Signals Absolute23. Processor Core Voltage Identification Code1 VID2 VID1 VID0State Transition Ramp Rate Comment 24. Processor Power StatesItanium 2 Processor System Bus Clock and Processor Clocking 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17#System Bus Reset and Configuration Timings for Cold Reset Pins/Pin Groups Recommended Recommended Connections for Unused Pins26. Connection for Unused Pins Sheet 1 TAP SignalsLvttl Power Pod Signals 26. Connection for Unused Pins Sheet 2System Management Signals Reserved PinsPinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal NamePin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/OutputPin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 LocationPin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor PackageProcessor Substrate UnitsItanium 2 Processor Package Power Tab Processor Bottom-Side Marking Package MarkingProcessor Top-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal AlertSymbol Parameter Core Minimum Maximum Unit Case TemperatureCase Temperature Specification Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications Signal Name Pin Count Description System Management Interface SignalsSystem Management Interface Signal Descriptions System Management BusSystem Management Feature Specifications SMBus Device Addressing 9XhProcessor Information ROM Format Sheet 1 Processor Information ROMEeprom SMBus Addressing on the Itanium 2 Processor Cache Processor Information ROM Format Sheet 2Offset Function Examples Section Bits Offset Function Examples Section Bits Package FeaturesProcessor Information ROM Format Sheet 3 Part NumbersOther Scratch EepromProcessor Information ROM Format Sheet 4 Random Address Read SMBus Packet Thermal Sensing DeviceCurrent Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions Thermal Sensing Device Registers 13. Command Byte Bit AssignmentRegister Command Reset State Function Thermal Reference RegistersThermal Limit Registers Configuration Register15. Thermal Sensing Device Configuration Register Status Register16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate HzConversion Rate Register Alphabetical Signals Reference BCLKp/BCLKn Table A-2. Effective Memory Type Signal EncodingATTR30# I/O 8 BE70# I/OBERR# I/O Table A-3. Special Transaction Encoding on Byte EnablesSpecial Transaction Byte Enables70# 12 BPM50# I/O BINIT# I/O11 BNR# I/O BPRI#BREQ30# I/O Table A-6. BR30# Signals and Agent IDsBus Signal Agent 0 Pins Agent 3 Pins Pin Sampled# I/O CCL# I/OD1270# I/O DBSYC1# O24 DEN# I/O DBSYC2# ODEFER# 25 DEP150# I/ODRDYC1# O 27 DPS# I/ODRDY# I/O DRDYC2# OHIT# I/O and HITM# I/O 33 FCL# I/OFERR# O ID90#Table A-9. Length of Data Transfers IP10#LEN20# I/O LEN20#PMI# LINT10OWN# I/O REQ50# I/OTransaction REQa50# REQb50# RESET#52 RP# I/O SBSYC1# O RS20#RSP# SBSYC2# OTHRMTRIP# O STBn70# and STBp70# I/OTDO O Table A-11. STBp70# and STBn70# AssociationsName Active Level Clock Signal Group Signal SummariesTable A-12. Output Signals Sheet 1 TND# I/OName Active Level Clock Signal Group Qualified Table A-12. Output Signals Sheet 2Table A-13. Input Signals Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver108