Intel Itanium 2 Processor manual Pin/Signal Information Sorted by Pin Location Sheet 7

Page 59

Pinout Specifications

Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 7 of 15)

Pin Name

System Bus

Pin

Input/Output

Notes

Signal Name

Location

 

 

 

 

 

 

 

 

D053#

D53#

L09

IN/OUT

 

 

 

 

 

 

D056#

D56#

L11

IN/OUT

 

 

 

 

 

 

VCTERM

VCTERM

L12

IN

 

 

 

 

 

 

D052#

D52#

L13

IN/OUT

 

 

 

 

 

 

D081#

D81#

L15

IN/OUT

 

 

 

 

 

 

VCTERM

VCTERM

L16

IN

 

 

 

 

 

 

D088#

D88#

L17

IN/OUT

 

 

 

 

 

 

D082#

D82#

L19

IN/OUT

 

 

 

 

 

 

VCTERM

VCTERM

L20

IN

 

 

 

 

 

 

D112#

D112#

L21

IN/OUT

 

 

 

 

 

 

D116#

D116#

L23

IN/OUT

 

 

 

 

 

 

VCTERM

VCTERM

L24

IN

 

 

 

 

 

 

D113#

D113#

L25

IN/OUT

 

 

 

 

 

 

GND

GND

M01

IN

 

 

 

 

 

 

D020#

D20#

M02

IN/OUT

 

 

 

 

 

 

GND

GND

M03

IN

 

 

 

 

 

 

STBP1#

STBP1#

M04

IN/OUT

 

 

 

 

 

 

GND

GND

M05

IN

 

 

 

 

 

 

D028#

D28#

M06

IN/OUT

 

 

 

 

 

 

GND

GND

M07

IN

 

 

 

 

 

 

D048#

D48#

M08

IN/OUT

 

 

 

 

 

 

GND

GND

M09

IN

 

 

 

 

 

 

STBP3#

STBP3#

M10

IN/OUT

 

 

 

 

 

 

GND

GND

M11

IN

 

 

 

 

 

 

D051#

D51#

M12

IN/OUT

 

 

 

 

 

 

GND

GND

M13

IN

 

 

 

 

 

 

D084#

D84#

M14

IN/OUT

 

 

 

 

 

 

GND

GND

M15

IN

 

 

 

 

 

 

STBP5#

STBP5#

M16

IN/OUT

 

 

 

 

 

 

GND

GND

M17

IN

 

 

 

 

 

 

D086#

D86#

M18

IN/OUT

 

 

 

 

 

 

GND

GND

M19

IN

 

 

 

 

 

 

D118#

D118#

M20

IN/OUT

 

 

 

 

 

 

GND

GND

M21

IN

 

 

 

 

 

 

STBP7#

STBP7#

M22

IN/OUT

 

 

 

 

 

 

GND

GND

M23

IN

 

 

 

 

 

 

D115#

D115#

M24

IN/OUT

 

 

 

 

 

 

GND

GND

M25

IN

 

 

 

 

 

 

VCTERM

VCTERM

N02

IN

 

 

 

 

 

 

D023#

D23#

N03

IN/OUT

 

 

 

 

 

 

GND

GND

N04

IN

 

 

 

 

 

 

Datasheet

59

Image 59
Contents Intel Itanium 2 Processor DatasheetDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures BINIT#, HIT#, HITM#, BNR#, TND#, BERR# Tables106 Revision No Description Date Revision HistoryIntel Itanium 2 Processor Product FeaturesDatasheet Processor Abstraction Layer OverviewState of Data Mixing Processors of Different Frequencies and Cache SizesTerminology Title Document Number Reference DocumentsIntroduction Itanium 2 Processor System Bus System Bus SignalsSystem Bus Power Pins Signal GroupsGroup Name Signals Signal DescriptionsItanium 2 Processor System Bus Signal Groups Symbol Parameter Core Minimum Typ Maximum Unit Package SpecificationsItanium 2 Processor Package Specifications Symbol Parameter Minimum Typ Maximum Unit Signal SpecificationsItanium 2 Processor Power Supply Specifications AGTL+ Signals DC Specifications Sheet 1TAP Connection DC Specifications AGTL+ Signals DC Specifications Sheet 2Power Good Signal DC Specifications System Bus Clock Differential Hstl DC SpecificationsMinimum Typ Maximum Unit SMBus DC SpecificationsLvttl Signal DC Specifications System Symbol ParameterMinimum Typ Maximum 11. SMBus AC Specifications12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1 Maximum Ratings12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2 Overshoot/Undershoot MagnitudeActivity Factor Overshoot/Undershoot Pulse DurationVcterm Reading Overshoot/Undershoot Specification TablesAF = 1 Shoot Parameter Description Specification UnitsAbsolute Pulse Duration ns Over0143 Wired-OR Signals 0513 Absolute Power Pod Connector Signals22. Itanium 2 Processor Power Pod Connector Signals Group Name Signals Power Pod ConnectorVID2 VID1 VID0 23. Processor Core Voltage Identification Code1State Transition Ramp Rate Comment 24. Processor Power StatesItanium 2 Processor System Bus Clock and Processor Clocking Ratio of Bus Frequency A21# A20# A19# A18# A17# 25. Itanium 2 Processor System Bus RatiosSystem Bus Reset and Configuration Timings for Cold Reset TAP Signals Recommended Connections for Unused Pins26. Connection for Unused Pins Sheet 1 Pins/Pin Groups RecommendedReserved Pins 26. Connection for Unused Pins Sheet 2System Management Signals Lvttl Power Pod SignalsPinout Specifications Pin Name System Bus Input/Output Signal Name Pin/Signal Information Sorted by Pin Name Sheet 1Pin Name System Bus Input/Output Pin/Signal Information Sorted by Pin Name Sheet 2Pin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Location Pin/Signal Information Sorted by Pin Location Sheet 1Pin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Itanium 2 Processor Package Mechanical DimensionsSubstrate Units ProcessorItanium 2 Processor Package Power Tab Processor Bottom-Side Marking Package MarkingProcessor Top-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Alert Thermal FeaturesEnhanced Thermal Management Case TemperatureCase Temperature Specification Symbol Parameter Core Minimum Maximum UnitItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Bus System Management Interface SignalsSystem Management Interface Signal Descriptions Signal Name Pin Count DescriptionSystem Management Feature Specifications 9Xh SMBus Device AddressingProcessor Information ROM Format Sheet 1 Processor Information ROMEeprom SMBus Addressing on the Itanium 2 Processor Cache Processor Information ROM Format Sheet 2Offset Function Examples Section Bits Part Numbers FeaturesProcessor Information ROM Format Sheet 3 Offset Function Examples Section Bits PackageOther Scratch EepromProcessor Information ROM Format Sheet 4 Byte Write SMBus Packet Thermal Sensing DeviceCurrent Address Read SMBus Packet Random Address Read SMBus PacketThermal Sensing Device Supported SMBus Transactions Thermal Reference Registers 13. Command Byte Bit AssignmentRegister Command Reset State Function Thermal Sensing Device RegistersStatus Register Configuration Register15. Thermal Sensing Device Configuration Register Thermal Limit Registers16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate HzConversion Rate Register Alphabetical Signals Reference 8 BE70# I/O Table A-2. Effective Memory Type Signal EncodingATTR30# I/O BCLKp/BCLKnBERR# I/O Table A-3. Special Transaction Encoding on Byte EnablesSpecial Transaction Byte Enables70# BPRI# BINIT# I/O11 BNR# I/O 12 BPM50# I/OPin Sampled Table A-6. BR30# Signals and Agent IDsBus Signal Agent 0 Pins Agent 3 Pins BREQ30# I/ODBSYC1# O CCL# I/OD1270# I/O # I/O25 DEP150# I/O DBSYC2# ODEFER# 24 DEN# I/ODRDYC2# O 27 DPS# I/ODRDY# I/O DRDYC1# OID90# 33 FCL# I/OFERR# O HIT# I/O and HITM# I/OLEN20# IP10#LEN20# I/O Table A-9. Length of Data TransfersREQ50# I/O LINT10OWN# I/O PMI#Transaction REQa50# REQb50# RESET#52 RP# I/O SBSYC2# O RS20#RSP# SBSYC1# OTable A-11. STBp70# and STBn70# Associations STBn70# and STBp70# I/OTDO O THRMTRIP# OTND# I/O Signal SummariesTable A-12. Output Signals Sheet 1 Name Active Level Clock Signal GroupName Active Level Clock Signal Group Qualified Table A-12. Output Signals Sheet 2Table A-13. Input Signals Table A-15. Input/Output Signals Multiple Driver Table A-14. Input/Output Signals Single Driver108