Intel Itanium 2 Processor manual Pin/Signal Information Sorted by Pin Name Sheet 9

Page 46

Pinout Specifications

Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 9 of 15)

Pin Name

System Bus

Pin

Input/Output

Notes

Signal Name

Location

 

 

 

 

 

 

 

 

GND

GND

F01

IN

 

 

 

 

 

 

GND

GND

F03

IN

 

 

 

 

 

 

GND

GND

F05

IN

 

 

 

 

 

 

GND

GND

F07

IN

 

 

 

 

 

 

GND

GND

F09

IN

 

 

 

 

 

 

GND

GND

F11

IN

 

 

 

 

 

 

GND

GND

F13

IN

 

 

 

 

 

 

GND

GND

F15

IN

 

 

 

 

 

 

GND

GND

F17

IN

 

 

 

 

 

 

GND

GND

F19

IN

 

 

 

 

 

 

GND

GND

F21

IN

 

 

 

 

 

 

GND

GND

F23

IN

 

 

 

 

 

 

GND

GND

F25

IN

 

 

 

 

 

 

GND

GND

G02

IN

 

 

 

 

 

 

GND

GND

H03

IN

 

 

 

 

 

 

GND

GND

H05

IN

 

 

 

 

 

 

GND

GND

H07

IN

 

 

 

 

 

 

GND

GND

H09

IN

 

 

 

 

 

 

GND

GND

H11

IN

 

 

 

 

 

 

GND

GND

H13

IN

 

 

 

 

 

 

GND

GND

H15

IN

 

 

 

 

 

 

GND

GND

H17

IN

 

 

 

 

 

 

GND

GND

H19

IN

 

 

 

 

 

 

GND

GND

H21

IN

 

 

 

 

 

 

GND

GND

H23

IN

 

 

 

 

 

 

GND

GND

H25

IN

 

 

 

 

 

 

GND

GND

J01

IN

 

 

 

 

 

 

GND

GND

J04

IN

 

 

 

 

 

 

GND

GND

J08

IN

 

 

 

 

 

 

GND

GND

J12

IN

 

 

 

 

 

 

GND

GND

J16

IN

 

 

 

 

 

 

GND

GND

J20

IN

 

 

 

 

 

 

GND

GND

J24

IN

 

 

 

 

 

 

GND

GND

K03

IN

 

 

 

 

 

 

GND

GND

K05

IN

 

 

 

 

 

 

GND

GND

K07

IN

 

 

 

 

 

 

GND

GND

K09

IN

 

 

 

 

 

 

GND

GND

K11

IN

 

 

 

 

 

 

GND

GND

K13

IN

 

 

 

 

 

 

GND

GND

K15

IN

 

 

 

 

 

 

GND

GND

K17

IN

 

 

 

 

 

 

46

Datasheet

Image 46
Contents Datasheet Intel Itanium 2 ProcessorDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR#106 Revision History Revision No Description DateProduct Features Intel Itanium 2 ProcessorDatasheet Overview Processor Abstraction LayerTerminology Mixing Processors of Different Frequencies and Cache SizesState of Data Reference Documents Title Document NumberIntroduction Signal Groups System Bus SignalsSystem Bus Power Pins Itanium 2 Processor System BusItanium 2 Processor System Bus Signal Groups Signal DescriptionsGroup Name Signals Itanium 2 Processor Package Specifications Package SpecificationsSymbol Parameter Core Minimum Typ Maximum Unit AGTL+ Signals DC Specifications Sheet 1 Signal SpecificationsItanium 2 Processor Power Supply Specifications Symbol Parameter Minimum Typ Maximum UnitSystem Bus Clock Differential Hstl DC Specifications AGTL+ Signals DC Specifications Sheet 2Power Good Signal DC Specifications TAP Connection DC SpecificationsSystem Symbol Parameter SMBus DC SpecificationsLvttl Signal DC Specifications Minimum Typ Maximum Unit11. SMBus AC Specifications Minimum Typ MaximumMaximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2Overshoot/Undershoot Pulse Duration Activity FactorReading Overshoot/Undershoot Specification Tables VctermOver Parameter Description Specification UnitsAbsolute Pulse Duration ns AF = 1 Shoot0143 Wired-OR Signals 0513 Group Name Signals Power Pod Connector Power Pod Connector Signals22. Itanium 2 Processor Power Pod Connector Signals Absolute23. Processor Core Voltage Identification Code1 VID2 VID1 VID0Itanium 2 Processor System Bus Clock and Processor Clocking 24. Processor Power StatesState Transition Ramp Rate Comment 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17#System Bus Reset and Configuration Timings for Cold Reset Pins/Pin Groups Recommended Recommended Connections for Unused Pins26. Connection for Unused Pins Sheet 1 TAP SignalsLvttl Power Pod Signals 26. Connection for Unused Pins Sheet 2System Management Signals Reserved PinsPinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal NamePin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/OutputPin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 LocationPin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor PackageProcessor Substrate UnitsItanium 2 Processor Package Power Tab Processor Top-Side Marking Package MarkingProcessor Bottom-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal AlertSymbol Parameter Core Minimum Maximum Unit Case TemperatureCase Temperature Specification Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications Signal Name Pin Count Description System Management Interface SignalsSystem Management Interface Signal Descriptions System Management BusSystem Management Feature Specifications SMBus Device Addressing 9XhEeprom SMBus Addressing on the Itanium 2 Processor Processor Information ROMProcessor Information ROM Format Sheet 1 Offset Function Examples Section Bits Processor Information ROM Format Sheet 2Cache Offset Function Examples Section Bits Package FeaturesProcessor Information ROM Format Sheet 3 Part NumbersProcessor Information ROM Format Sheet 4 Scratch EepromOther Random Address Read SMBus Packet Thermal Sensing DeviceCurrent Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions Thermal Sensing Device Registers 13. Command Byte Bit AssignmentRegister Command Reset State Function Thermal Reference RegistersThermal Limit Registers Configuration Register15. Thermal Sensing Device Configuration Register Status RegisterConversion Rate Register Register Contents Conversion Rate Hz16. Thermal Sensing Device Conversion Rate Register Alphabetical Signals Reference BCLKp/BCLKn Table A-2. Effective Memory Type Signal EncodingATTR30# I/O 8 BE70# I/OSpecial Transaction Byte Enables70# Table A-3. Special Transaction Encoding on Byte EnablesBERR# I/O 12 BPM50# I/O BINIT# I/O11 BNR# I/O BPRI#BREQ30# I/O Table A-6. BR30# Signals and Agent IDsBus Signal Agent 0 Pins Agent 3 Pins Pin Sampled# I/O CCL# I/OD1270# I/O DBSYC1# O24 DEN# I/O DBSYC2# ODEFER# 25 DEP150# I/ODRDYC1# O 27 DPS# I/ODRDY# I/O DRDYC2# OHIT# I/O and HITM# I/O 33 FCL# I/OFERR# O ID90#Table A-9. Length of Data Transfers IP10#LEN20# I/O LEN20#PMI# LINT10OWN# I/O REQ50# I/O52 RP# I/O RESET#Transaction REQa50# REQb50# SBSYC1# O RS20#RSP# SBSYC2# OTHRMTRIP# O STBn70# and STBp70# I/OTDO O Table A-11. STBp70# and STBn70# AssociationsName Active Level Clock Signal Group Signal SummariesTable A-12. Output Signals Sheet 1 TND# I/OTable A-13. Input Signals Table A-12. Output Signals Sheet 2Name Active Level Clock Signal Group Qualified Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver108