Intel Itanium 2 Processor manual Thermal Sensing Device Supported SMBus Transactions

Page 87

System Management Feature Specifications

THRMALERT# signal (see Section 6.1.1 for more details). At power up, the appropriate alarm register values need to be programmed into the thermal sensing device via the SMBus. It is recommended that the upper thermal reference threshold byte (provided in the processor information ROM) be used for setting the upper threshold value in the alarm register.

When polling the thermal sensing device on the processor to read the processor temperatures, it is recommended that the polling frequency be every 0.5 to 1 second.

6.6Thermal Sensing Device Supported SMBus Transactions

The thermal sensing device responds to five of the SMBus packet types: write byte, read byte, send byte, receive byte, and alert response address (ARA). The send byte packet is used for sending one- shot commands only. The receive byte packet accesses the register commanded by the last read byte packet. If a receive byte packet was preceded by a write byte or send byte packet more recently than a read byte packet, then the behavior is undefined. Table 6-8through Table 6-12diagram the five packet types. In these tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an acknowledge, and ‘///’ represents a negative acknowledge. The shaded bits are transmitted by the thermal sensor and the unshaded bits are transmitted by the SMBus host controller. Table 6-13shows the encoding of the command byte.

Table 6-8. Write Byte SMBus Packet

S

Address

Write

Ack

Command

Ack

Data

Ack

P

 

 

 

 

 

 

 

 

 

1

7 bits

1

1

8 bits

1

8 bits

1

1

 

 

 

 

 

 

 

 

 

Table 6-9. Read Byte SMBus Packet

S

Address

Write

Ack

Command

Ack

S

Address

Read

Ack

Data

///

P

 

 

 

 

 

 

 

 

 

 

 

 

 

1

7 bits

1

1

8 bits

1

1

7 bits

1

1

8 bits

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6-10. Send Byte SMBus Packet

S

Address

Write

Ack

Command

Ack

P

 

 

 

 

 

 

 

1

7 bits

1

1

8 bits

1

 

 

 

 

 

 

 

 

Table 6-11. Receive Byte SMBus Packet

S

Address

Read

Ack

Data

///

P

 

 

 

 

 

 

 

1

7 bits

1

1

8 bits

1

1

 

 

 

 

 

 

 

Table 6-12. ARA SMBus Packet

S

ARA

Read

Ack

Address

///

P

 

 

 

 

 

 

 

1

0001 100

1

1

1001 1011

1

1

 

 

 

 

 

 

 

Datasheet

87

Image 87
Contents Intel Itanium 2 Processor DatasheetDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures BINIT#, HIT#, HITM#, BNR#, TND#, BERR# Tables106 Revision No Description Date Revision HistoryIntel Itanium 2 Processor Product FeaturesDatasheet Processor Abstraction Layer OverviewMixing Processors of Different Frequencies and Cache Sizes TerminologyState of Data Title Document Number Reference DocumentsIntroduction Itanium 2 Processor System Bus System Bus SignalsSystem Bus Power Pins Signal GroupsSignal Descriptions Itanium 2 Processor System Bus Signal GroupsGroup Name Signals Package Specifications Itanium 2 Processor Package SpecificationsSymbol Parameter Core Minimum Typ Maximum Unit Symbol Parameter Minimum Typ Maximum Unit Signal SpecificationsItanium 2 Processor Power Supply Specifications AGTL+ Signals DC Specifications Sheet 1TAP Connection DC Specifications AGTL+ Signals DC Specifications Sheet 2Power Good Signal DC Specifications System Bus Clock Differential Hstl DC SpecificationsMinimum Typ Maximum Unit SMBus DC SpecificationsLvttl Signal DC Specifications System Symbol ParameterMinimum Typ Maximum 11. SMBus AC Specifications12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1 Maximum Ratings12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2 Overshoot/Undershoot MagnitudeActivity Factor Overshoot/Undershoot Pulse DurationVcterm Reading Overshoot/Undershoot Specification TablesAF = 1 Shoot Parameter Description Specification UnitsAbsolute Pulse Duration ns Over0143 Wired-OR Signals 0513 Absolute Power Pod Connector Signals22. Itanium 2 Processor Power Pod Connector Signals Group Name Signals Power Pod ConnectorVID2 VID1 VID0 23. Processor Core Voltage Identification Code124. Processor Power States Itanium 2 Processor System Bus Clock and Processor ClockingState Transition Ramp Rate Comment Ratio of Bus Frequency A21# A20# A19# A18# A17# 25. Itanium 2 Processor System Bus RatiosSystem Bus Reset and Configuration Timings for Cold Reset TAP Signals Recommended Connections for Unused Pins26. Connection for Unused Pins Sheet 1 Pins/Pin Groups RecommendedReserved Pins 26. Connection for Unused Pins Sheet 2System Management Signals Lvttl Power Pod SignalsPinout Specifications Pin Name System Bus Input/Output Signal Name Pin/Signal Information Sorted by Pin Name Sheet 1Pin Name System Bus Input/Output Pin/Signal Information Sorted by Pin Name Sheet 2Pin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Location Pin/Signal Information Sorted by Pin Location Sheet 1Pin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Itanium 2 Processor Package Mechanical DimensionsSubstrate Units ProcessorItanium 2 Processor Package Power Tab Package Marking Processor Top-Side MarkingProcessor Bottom-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Alert Thermal FeaturesEnhanced Thermal Management Case TemperatureCase Temperature Specification Symbol Parameter Core Minimum Maximum UnitItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Bus System Management Interface SignalsSystem Management Interface Signal Descriptions Signal Name Pin Count DescriptionSystem Management Feature Specifications 9Xh SMBus Device AddressingProcessor Information ROM Eeprom SMBus Addressing on the Itanium 2 ProcessorProcessor Information ROM Format Sheet 1 Processor Information ROM Format Sheet 2 Offset Function Examples Section BitsCache Part Numbers FeaturesProcessor Information ROM Format Sheet 3 Offset Function Examples Section Bits PackageScratch Eeprom Processor Information ROM Format Sheet 4Other Byte Write SMBus Packet Thermal Sensing DeviceCurrent Address Read SMBus Packet Random Address Read SMBus PacketThermal Sensing Device Supported SMBus Transactions Thermal Reference Registers 13. Command Byte Bit AssignmentRegister Command Reset State Function Thermal Sensing Device RegistersStatus Register Configuration Register15. Thermal Sensing Device Configuration Register Thermal Limit RegistersRegister Contents Conversion Rate Hz Conversion Rate Register16. Thermal Sensing Device Conversion Rate Register Alphabetical Signals Reference 8 BE70# I/O Table A-2. Effective Memory Type Signal EncodingATTR30# I/O BCLKp/BCLKnTable A-3. Special Transaction Encoding on Byte Enables Special Transaction Byte Enables70#BERR# I/O BPRI# BINIT# I/O11 BNR# I/O 12 BPM50# I/OPin Sampled Table A-6. BR30# Signals and Agent IDsBus Signal Agent 0 Pins Agent 3 Pins BREQ30# I/ODBSYC1# O CCL# I/OD1270# I/O # I/O25 DEP150# I/O DBSYC2# ODEFER# 24 DEN# I/ODRDYC2# O 27 DPS# I/ODRDY# I/O DRDYC1# OID90# 33 FCL# I/OFERR# O HIT# I/O and HITM# I/OLEN20# IP10#LEN20# I/O Table A-9. Length of Data TransfersREQ50# I/O LINT10OWN# I/O PMI#RESET# 52 RP# I/OTransaction REQa50# REQb50# SBSYC2# O RS20#RSP# SBSYC1# OTable A-11. STBp70# and STBn70# Associations STBn70# and STBp70# I/OTDO O THRMTRIP# OTND# I/O Signal SummariesTable A-12. Output Signals Sheet 1 Name Active Level Clock Signal GroupTable A-12. Output Signals Sheet 2 Table A-13. Input SignalsName Active Level Clock Signal Group Qualified Table A-15. Input/Output Signals Multiple Driver Table A-14. Input/Output Signals Single Driver108