Intel Itanium 2 Processor manual Pin/Signal Information Sorted by Pin Name Sheet 3

Page 40

Pinout Specifications

Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 3 of 15)

Pin Name

System Bus

Pin

Input/Output

Notes

Signal Name

Location

 

 

 

 

 

 

 

 

D010#

D10#

E07

IN/OUT

 

 

 

 

 

 

D011#

D11#

H02

IN/OUT

 

 

 

 

 

 

D012#

D12#

H04

IN/OUT

 

 

 

 

 

 

D013#

D13#

J03

IN/OUT

 

 

 

 

 

 

D014#

D14#

G03

IN/OUT

 

 

 

 

 

 

D015#

D15#

G07

IN/OUT

 

 

 

 

 

 

D016#

D16#

K04

IN/OUT

 

 

 

 

 

 

D017#

D17#

L03

IN/OUT

 

 

 

 

 

 

D018#

D18#

K06

IN/OUT

 

 

 

 

 

 

D019#

D19#

L05

IN/OUT

 

 

 

 

 

 

D020#

D20#

M02

IN/OUT

 

 

 

 

 

 

D021#

D21#

L07

IN/OUT

 

 

 

 

 

 

D022#

D22#

N07

IN/OUT

 

 

 

 

 

 

D023#

D23#

N03

IN/OUT

 

 

 

 

 

 

D024#

D24#

P04

IN/OUT

 

 

 

 

 

 

D025#

D25#

R03

IN/OUT

 

 

 

 

 

 

D026#

D26#

P06

IN/OUT

 

 

 

 

 

 

D027#

D27#

P02

IN/OUT

 

 

 

 

 

 

D028#

D28#

M06

IN/OUT

 

 

 

 

 

 

D029#

D29#

R05

IN/OUT

 

 

 

 

 

 

D030#

D30#

T02

IN/OUT

 

 

 

 

 

 

D031#

D31#

R07

IN/OUT

 

 

 

 

 

 

D032#

D32#

H10

IN/OUT

 

 

 

 

 

 

D033#

D33#

C11

IN/OUT

 

 

 

 

 

 

D034#

D34#

D10

IN/OUT

 

 

 

 

 

 

D035#

D35#

C09

IN/OUT

 

 

 

 

 

 

D036#

D36#

D12

IN/OUT

 

 

 

 

 

 

D037#

D37#

D08

IN/OUT

 

 

 

 

 

 

D038#

D38#

G09

IN/OUT

 

 

 

 

 

 

D039#

D39#

E13

IN/OUT

 

 

 

 

 

 

D040#

D40#

E09

IN/OUT

 

 

 

 

 

 

D041#

D41#

G11

IN/OUT

 

 

 

 

 

 

D042#

D42#

H08

IN/OUT

 

 

 

 

 

 

D043#

D43#

G13

IN/OUT

 

 

 

 

 

 

D044#

D44#

F12

IN/OUT

 

 

 

 

 

 

D045#

D45#

F08

IN/OUT

 

 

 

 

 

 

D046#

D46#

H12

IN/OUT

 

 

 

 

 

 

D047#

D47#

J13

IN/OUT

 

 

 

 

 

 

D048#

D48#

M08

IN/OUT

 

 

 

 

 

 

D049#

D49#

K08

IN/OUT

 

 

 

 

 

 

D050#

D50#

K10

IN/OUT

 

 

 

 

 

 

40

Datasheet

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Contents Datasheet Intel Itanium 2 ProcessorDatasheet Contents Processor Information ROM and Scratch Eeprom Supported Figures Tables BINIT#, HIT#, HITM#, BNR#, TND#, BERR#106 Revision History Revision No Description DateProduct Features Intel Itanium 2 ProcessorDatasheet Overview Processor Abstraction LayerTerminology Mixing Processors of Different Frequencies and Cache SizesState of Data Reference Documents Title Document NumberIntroduction System Bus Signals System Bus Power PinsSignal Groups Itanium 2 Processor System BusItanium 2 Processor System Bus Signal Groups Signal DescriptionsGroup Name Signals Itanium 2 Processor Package Specifications Package SpecificationsSymbol Parameter Core Minimum Typ Maximum Unit Signal Specifications Itanium 2 Processor Power Supply SpecificationsAGTL+ Signals DC Specifications Sheet 1 Symbol Parameter Minimum Typ Maximum UnitAGTL+ Signals DC Specifications Sheet 2 Power Good Signal DC SpecificationsSystem Bus Clock Differential Hstl DC Specifications TAP Connection DC SpecificationsSMBus DC Specifications Lvttl Signal DC SpecificationsSystem Symbol Parameter Minimum Typ Maximum Unit11. SMBus AC Specifications Minimum Typ MaximumMaximum Ratings 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 1Overshoot/Undershoot Magnitude 12. Itanium 2 Processor Absolute Maximum Ratings Sheet 2Overshoot/Undershoot Pulse Duration Activity FactorReading Overshoot/Undershoot Specification Tables VctermParameter Description Specification Units Absolute Pulse Duration nsOver AF = 1 Shoot0143 Wired-OR Signals 0513 Power Pod Connector Signals 22. Itanium 2 Processor Power Pod Connector SignalsGroup Name Signals Power Pod Connector Absolute23. Processor Core Voltage Identification Code1 VID2 VID1 VID0Itanium 2 Processor System Bus Clock and Processor Clocking 24. Processor Power StatesState Transition Ramp Rate Comment 25. Itanium 2 Processor System Bus Ratios Ratio of Bus Frequency A21# A20# A19# A18# A17#System Bus Reset and Configuration Timings for Cold Reset Recommended Connections for Unused Pins 26. Connection for Unused Pins Sheet 1Pins/Pin Groups Recommended TAP Signals26. Connection for Unused Pins Sheet 2 System Management SignalsLvttl Power Pod Signals Reserved PinsPinout Specifications Pin/Signal Information Sorted by Pin Name Sheet 1 Pin Name System Bus Input/Output Signal NamePin/Signal Information Sorted by Pin Name Sheet 2 Pin Name System Bus Input/OutputPin/Signal Information Sorted by Pin Name Sheet 3 Pin/Signal Information Sorted by Pin Name Sheet 4 Pin/Signal Information Sorted by Pin Name Sheet 5 Pin/Signal Information Sorted by Pin Name Sheet 6 Pin/Signal Information Sorted by Pin Name Sheet 7 Pin/Signal Information Sorted by Pin Name Sheet 8 Pin/Signal Information Sorted by Pin Name Sheet 9 Pin/Signal Information Sorted by Pin Name Sheet 10 Pin/Signal Information Sorted by Pin Name Sheet 11 Pin/Signal Information Sorted by Pin Name Sheet 12 Pin/Signal Information Sorted by Pin Name Sheet 13 Pin/Signal Information Sorted by Pin Name Sheet 14 Pin/Signal Information Sorted by Pin Name Sheet 15 Pin/Signal Information Sorted by Pin Location Sheet 1 LocationPin/Signal Information Sorted by Pin Location Sheet 2 Pin/Signal Information Sorted by Pin Location Sheet 3 Pin/Signal Information Sorted by Pin Location Sheet 4 Pin/Signal Information Sorted by Pin Location Sheet 5 Pin/Signal Information Sorted by Pin Location Sheet 6 Pin/Signal Information Sorted by Pin Location Sheet 7 Pin/Signal Information Sorted by Pin Location Sheet 8 Pin/Signal Information Sorted by Pin Location Sheet 9 Pin/Signal Information Sorted by Pin Location Sheet 10 Pin/Signal Information Sorted by Pin Location Sheet 11 Pin/Signal Information Sorted by Pin Location Sheet 12 Pin/Signal Information Sorted by Pin Location Sheet 13 Pin/Signal Information Sorted by Pin Location Sheet 14 Pin/Signal Information Sorted by Pin Location Sheet 15 Pinout Specifications Mechanical Dimensions Itanium 2 Processor PackageProcessor Substrate UnitsItanium 2 Processor Package Power Tab Processor Top-Side Marking Package MarkingProcessor Bottom-Side Marking Processor Bottom-Side Marking Placement on Interposer Mechanical Specifications Thermal Features Thermal AlertCase Temperature Case Temperature SpecificationSymbol Parameter Core Minimum Maximum Unit Enhanced Thermal ManagementItanium 2 Processor Package Thermocouple Location Thermal Specifications System Management Interface Signals System Management Interface Signal DescriptionsSignal Name Pin Count Description System Management BusSystem Management Feature Specifications SMBus Device Addressing 9XhEeprom SMBus Addressing on the Itanium 2 Processor Processor Information ROMProcessor Information ROM Format Sheet 1 Offset Function Examples Section Bits Processor Information ROM Format Sheet 2Cache Features Processor Information ROM Format Sheet 3Offset Function Examples Section Bits Package Part NumbersProcessor Information ROM Format Sheet 4 Scratch EepromOther Thermal Sensing Device Current Address Read SMBus PacketRandom Address Read SMBus Packet Byte Write SMBus PacketThermal Sensing Device Supported SMBus Transactions 13. Command Byte Bit Assignment Register Command Reset State FunctionThermal Sensing Device Registers Thermal Reference RegistersConfiguration Register 15. Thermal Sensing Device Configuration RegisterThermal Limit Registers Status RegisterConversion Rate Register Register Contents Conversion Rate Hz16. Thermal Sensing Device Conversion Rate Register Alphabetical Signals Reference Table A-2. Effective Memory Type Signal Encoding ATTR30# I/OBCLKp/BCLKn 8 BE70# I/OSpecial Transaction Byte Enables70# Table A-3. Special Transaction Encoding on Byte EnablesBERR# I/O BINIT# I/O 11 BNR# I/O12 BPM50# I/O BPRI#Table A-6. BR30# Signals and Agent IDs Bus Signal Agent 0 Pins Agent 3 PinsBREQ30# I/O Pin SampledCCL# I/O D1270# I/O# I/O DBSYC1# ODBSYC2# O DEFER#24 DEN# I/O 25 DEP150# I/O27 DPS# I/O DRDY# I/ODRDYC1# O DRDYC2# O33 FCL# I/O FERR# OHIT# I/O and HITM# I/O ID90#IP10# LEN20# I/OTable A-9. Length of Data Transfers LEN20#LINT10 OWN# I/OPMI# REQ50# I/O52 RP# I/O RESET#Transaction REQa50# REQb50# RS20# RSP#SBSYC1# O SBSYC2# OSTBn70# and STBp70# I/O TDO OTHRMTRIP# O Table A-11. STBp70# and STBn70# AssociationsSignal Summaries Table A-12. Output Signals Sheet 1Name Active Level Clock Signal Group TND# I/OTable A-13. Input Signals Table A-12. Output Signals Sheet 2Name Active Level Clock Signal Group Qualified Table A-14. Input/Output Signals Single Driver Table A-15. Input/Output Signals Multiple Driver108
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