System Management Feature Specifications
Table 6-4. Processor Information ROM Format (Sheet 2 of 4)
Offset/ | # of | Function | Notes |
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Section | Bits |
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09h | 8 | Feature Data Address | Byte pointer, 00h if not present | 67h |
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0Ah | 8 | Other Data Address | Byte pointer, 00h if not present | 7Ah |
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0Bh | 16 | Reserved | Reserved for future use | 0000h | |
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0Dh | 8 | Checksum | 1 byte checksum | Add up by byte and | |
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| take 2’s complement. | |
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Processor |
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0Eh | 48 | Six | |||
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| would be: | |
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| • | 13h = 00h |
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| • | 12h = 00h |
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| • | 11h = “3” |
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| • | 10h = “2” |
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| • | 0Fh = “1” |
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| • | 0Eh = “S” |
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14h | 2 | Sample/Production | 00b = Sample only (MSB First) | 00000001b = | |
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| Production | |
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15h | 8 | Reserved | Reserved for future use | 00h |
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16h | 8 | Checksum | 1 byte checksum | Add up by byte and | |
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| take 2’s complement. | |
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Core |
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17h | 8 | Architecture Revision | From CPUID1 | Taken from | |
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| CPUID[3].archrev. | |
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18h | 8 | Processor Core Family | From CPUID | Taken from | |
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| CPUID[3].family. | |
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19h | 8 | Processor Core Model | From CPUID | Taken from | |
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| CPUID[3].model. | |
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1Ah | 8 | Processor Core Stepping | From CPUID | Taken from | |
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| CPUID[3].revision. | |
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1Bh | 24 | Reserved | Reserved for future use | 000000h | |
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1Eh | 16 | Maximum Core Frequency | Four | 1 GHz = 1000h 2 | |
20h | 12 | Maximum System Bus | Three | 200 MHz = 200h 1 | |
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22h | 16 | Core Voltage ID | Voltage in four | 1500 mV = 1500h 1 | |
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24h | 8 | Core Voltage Tolerance, | Edge finger tolerance in mV, + | 1.5% = 22 mV = 22h 1 | |
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| High | two |
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25h | 8 | Core Voltage Tolerance, | Edge finger tolerance in mV, – | 1.5% = 22 mV = 22h 1 | |
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| Low | two |
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26h | 8 | Reserved | Reserved for future use | 00h |
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27h | 8 | Checksum | 1 byte checksum | Add up by byte and | |
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| take 2’s complement. | |
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Cache |
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28h | 32 | Reserved | Reserved for future use | 00000000h | |
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2Ch | 16 | Cache Size | Four | 3072 Kbytes = 3072h 1 | |
2Eh | 64 | Reserved | Reserved for future use | x0h |
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36h | 8 | Checksum | 1 byte checksum |
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Datasheet | 83 |