Intel 31244 PCI-X manual PCI-X Bus Pin Descriptions Sheet 2, Configuration Pin Descriptions

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Intel® 31244 PCI-X to Serial ATA Controller

Intel® 31244 PCI-X to Serial ATA Controller Package

Table 4.

PCI-X Bus Pin Descriptions (Sheet 2 of 2)

 

 

 

 

Name

Description

 

 

 

 

 

BIDIRECTIONAL - LVTTL: Indicates the attempt of a 64-bit transaction on the PCI bus.

 

P_REQ64#

When the target is 64-bit capable, the target acknowledges the attempt with the assertion of

 

 

P_ACK64#.

 

 

 

 

 

INPUT - LVTTL Reset: This signal is used to place PCI-X registers, sequencers, and

 

P_RST#

signals into a consistent state. When P_RST# is asserted, all PCI-X output signals are

 

 

tri-stated.

 

 

 

 

 

OUTPUT - Open Drain with Pull-Up Resistor: System Error. This signal is used to report

 

P_SERR#

address parity errors. When an error is detected, P_SERR# is driven LOW for a single

 

 

PCI-X clock.

 

 

 

 

 

BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Stop. This signal is driven by the target

 

P_STOP#

to indicate to the initiator that it wishes to stop the current transaction. As a bus slave,

 

P_STOP# is driven by the GD31244 to inform the bus master to stop the current transaction.

 

 

 

 

As a bus master, P_STOP# is received by the GD31244 to stop the current transaction.

 

 

 

 

 

BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Target Ready. This signal indicates the

 

P_TRDY#

selected device’s ability to complete the current data phase and is used in conjunction with

 

P_IRDY#. A data phase is completed on any clock cycle where both P_IRDY# and

 

 

 

 

P_TRDY# are asserted LOW.

 

 

 

 

TEST0

INPUT - LVTTL: Test input. Set LOW for normal operation.

 

 

 

 

TOUT

OUTPUT - Test pin. Do not use.

 

 

 

Table 5.

Configuration Pin Descriptions

 

 

 

 

 

Name

Type

Description

 

 

 

 

 

 

 

Pin number A2. This pin controls the state of the “64 bit device” status

 

32BITPCI#

INPUT

bit 16, in the PCI-X Status Register. When pulled down, reports a 0, a

 

 

 

32-bit bus. When pulled up, reports 1, a 64-bit device.

 

 

 

 

 

 

 

INPUT - LVTTL: When HIGH or open, selects Master/Slave Mode for

 

DPA_MODE#

INPUT

software compatibility. When LOW, selects Master-Master mode for

 

 

 

high performance.

 

 

 

 

 

SSCEN

INPUT

Tie this pin to GND.

 

 

 

 

Table 6.

JTAG Pin Descriptions

 

 

 

 

Name

Description

 

 

 

 

 

TEST DATA OUTPUT: is the serial output pin for the JTAG feature. TDO is driven on the

 

TDO

falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At

 

 

other times, TDO floats. The behavior of TDO is independent of P_RST#.

 

 

 

 

 

TEST DATA INPUT: is the serial input pin for the JTAG feature. TDI is sampled on the rising

 

TDI

edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal

 

 

has a weak internal pull-up to ensure proper operation when this signal is unconnected.

 

 

 

 

 

TEST CLOCK: is an input which provides the clocking function for the IEEE 1149.1

 

TCK

Boundary Scan Testing (JTAG). State information and data are clocked into the component

 

 

on the rising edge and data is clocked out of the component on the falling edge.

 

 

 

 

 

TEST MODE SELECT: is an input sampled at the rising edge of TCK to select the operation

 

TMS

of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal

 

 

pull-up to ensure proper operation when this signal is unconnected.

 

 

 

 

 

TEST RESET: an input that asynchronously resets the Test Access Port (TAP) controller

 

TRST#

function of IEEE 1149.1 Boundary Scan Testing (JTAG). This signal has a weak internal

 

 

pull-up.

 

 

 

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Design Guide

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Contents Intel 31244 PCI-X to Serial ATA Controller Design GuideIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Wire Lengths For Multiple PCI-X Load Embedded TablesRevision History Date Revision # DescriptionThis page intentionally left blank About This Document Reference DocumentationTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 Terminology and Definition Sheet 3 ISIThis page left intentionally blank Features OverviewPCI-X FifoApplications Quad Serial ATA Host Bus AdapterThis page left intentionally blank Intel 31244 PCI-X to Serial ATA Controller Package Packaging ConsiderationsName Description Signal Pin DescriptionsSerial ATA Signals Pin Descriptions PCI-X Bus Pin Descriptions Sheet 1 Jtag Pin Descriptions Configuration Pin DescriptionsPCI-X Bus Pin Descriptions Sheet 2 Serial ROM Interface Pin Descriptions Power Supply Pin Descriptions1 VA0, VA1 Vccpll Pin Requirements Package/Marking Information Package Information 256-pin PbgaBall Map By Function Pbga Mapped By Pin FunctionThis page left intentionally blank Routing Guidelines General Routing GuidelinesCrosstalk Crosstalk Effects on Trace Distance and HeightEMI Considerations Power Distribution and Decoupling DecouplingExample 1. Two-by-two Differential Impedance Matrix Trace ImpedanceDifferential Impedance Intel 31244 PCI-X to Serial ATA Controller Jtag Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsSerial ROM Interface PCI-X Interface Direct Port Access DPA Extended Voltage ModeNormal Voltage Mode Extended Voltage ModeLED LED0 LED1 LED InterfaceSDO LED SDI SCS# Sclk SCK Reference Clock Generation Load Capacitance 20 pF Shunt Capacitance 7 pFThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Extended Voltage Mode Intel 31244 PCI-X to Serial ATA Controller HBA StackupBackplane Topologies Write Backplane TopologyRead Backplane Topology Motherboard Stackup for Backplane Designs Motherboard Stackup, MicrostripMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Stripline Stackup Backplane Stripline StackupBackplane Stripline Stackup Cable Specification Cable Interconnect With BackplaneBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI/X Voltage Levels PCI-X Layout GuidelinesPCI Voltage Levels GND PCI/X Clocking ModesPCI-X Clocking Modes PCI General Layout Guidelines Add-on Card Routing ParametersMinimum Maximum CLKPCI-X Slot Guidelines PCI-X Layout Guidelines For Slot ConfigurationsProtection Circuitry for Add-in Cards PCI Clock Layout Guidelines Wiring Lengths for Single Slot Segment Lower AD Bus Upper AD BusLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Cables and Connectors Serial ATA Signal DefinitionsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Signal Connections Serial ATA CableVoltage Power Delivery This page left intentionally blank Parameter Min Max Test MethodologyInterface Timing and SI Requirements Serial ATA Eye Diagram Timing RequirementExtended Voltage Mode Receiver Model Extended Voltage Mode ReceiverExtended Voltage Mode Driver Model Extended Mode DriverPull-up or Pull-down Comments Terminations Pull-down/Pull-upsTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Logic Analyzer Pod 1 Sheet 1 Debug Connectors and Logic Analyzer Connectivity13Probing PCI-X Signals Logic Analyzer Pod 1 Sheet 2 Logic Analyzer PodIrdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Solutions Lead H-PBGA Package Thermal CharacteristicsThermal Recommendations Thermal ResistanceThis page left intentionally blank References Related DocumentsDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank