Intel 31244 PCI-X manual Trace Impedance, Differential Impedance

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4.5Trace Impedance

All signal layers require controlled impedance of 50 +/- 15%, microstrip or stripline where appropriate, unless otherwise specified. Selecting the appropriate board stack-up to minimize impedance variations is very important. When calculating flight times, it is important to consider the minimum and maximum trace impedance based on the switching neighboring traces. Use wider spaces between traces, since this may minimize trace-to-trace coupling, and reduce cross talk.

All recommendations described in this document assume a Twid 5 mil 50 signal trace, unless otherwise specified. When a different stack up is used the trace widths must be adjusted appropriately. When wider traces are used, the trace spacing must be adjusted accordingly (linearly).

It is highly recommended that a 2D Field Solver be used to design the high-speed traces. The following Impedance Calculator URLs provide approximations for the trace impedance of various topologies. They may be used to generate the starting point for a full 2D Field solver.

http://emclab.umr.edu/pcbtlc/

http://www.westak.com/techcenter/imped/

The following website link provides a useful basic guideline for calculating trace parameters:

http://www.ultracad.com/calc.htm

Note: Using stripline transmission lines may give better results than microstrip. This is due to the difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in limiting the plated thickness of microstrip conductors, which may substantially increase cross-talk.

4.5.1Differential Impedance

The Serial ATA standard defines a 100 ohms differential impedance. This section provides some basic background information on the differential impedance calculations. In the cross section of Figure 9 shows the cross section of two traces of a differential pair.

Figure 9. Cross Section of Differential Trace

Ground reference plane

To calculate the coupled impedance requires a 2x2 matrix. The diagonal values in the matrix represent the impedance of the traces to ground and the off-diagonal values provide a measure of how tightly the traces are coupled. The differential impedance is the value of the line-to-line resistor terminator that optimally terminates pure differential signals. The two by two matrix is shown below as:

Example 1. Two-by-two Differential Impedance Matrix

Zo =

Z11 Z12 Z21 Z22

Design Guide

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Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documentation About This DocumentTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageName Description Signal Pin DescriptionsSerial ATA Signals Pin Descriptions PCI-X Bus Pin Descriptions Sheet 1 Jtag Pin Descriptions Configuration Pin DescriptionsPCI-X Bus Pin Descriptions Sheet 2 Serial ROM Interface Pin Descriptions Power Supply Pin Descriptions1 VA0, VA1 Vccpll Pin Requirements Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingExample 1. Two-by-two Differential Impedance Matrix Trace ImpedanceDifferential Impedance Intel 31244 PCI-X to Serial ATA Controller Jtag Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsSerial ROM Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPANormal Voltage Mode Extended Voltage ModeLED LED0 LED1 LED InterfaceSDO LED SDI SCS# Sclk SCK Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Motherboard Stackup, Microstrip Motherboard Stackup for Backplane DesignsMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Stripline Stackup Backplane Stripline StackupBackplane Stripline Stackup Cable Interconnect With Backplane Cable SpecificationBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI/X Voltage Levels PCI-X Layout GuidelinesPCI Voltage Levels GND PCI/X Clocking ModesPCI-X Clocking Modes Add-on Card Routing Parameters PCI General Layout GuidelinesMinimum Maximum CLKPCI-X Slot Guidelines PCI-X Layout Guidelines For Slot ConfigurationsProtection Circuitry for Add-in Cards PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Signal Definitions Cables and ConnectorsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Parameter Min Max Test MethodologyInterface Timing and SI Requirements Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelPull-up or Pull-down Comments Terminations Pull-down/Pull-upsTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Logic Analyzer Pod 1 Sheet 1 Debug Connectors and Logic Analyzer Connectivity13Probing PCI-X Signals Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Lead H-PBGA Package Thermal Characteristics Thermal SolutionsThermal Recommendations Thermal ResistanceThis page left intentionally blank Related Documents ReferencesDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank