Intel 31244 PCI-X manual Lower AD Bus Upper AD Bus

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Intel® 31244 PCI-X to Serial ATA Controller

PCI-X Layout Guidelines

7.4.4Embedded Intel® 31244 PCI-X to Serial ATA Controller Single PCI-X Load

Figure 18 shows GD31244 as the PCI-X agent in a standalone embedded application (with no PCI-X slot). This figure shows one of the chipset PCI AD lines connected through W1 to the Intel® 31244 PCI-X to Serial ATA Controller. This AD line is also used as an IDSEL line from line segment W2 to a 2 K resistor through W3 to the GD31244 IDSEL line input buffer. Table 23 shows the corresponding wiring rules. These recommended wire lengths should support all PCI-X frequencies. However, prelayout simulation is recommended.

Figure 18. Embedded Intel® 31244 PCI-X to Serial ATA Controller

Design with Single PCI-X Load

 

W1

 

 

 

PCI

 

IDSEL

Agent

I/O Buffer

 

 

 

 

W2

W3

 

 

B0477-01

Table 23. Wiring Lengths for Embedded Intel® 31244 PCI-X to Serial ATA Controller with Single PCI-X Load

 

Lower AD Bus

Upper AD Bus

 

Segment

 

 

 

 

Units

 

Minimum Length

Maximum Length

Minimum Length

Maximum Length

 

 

 

 

 

 

 

W1

2.85

10

3.85

10.25

inches

 

 

 

 

 

 

W2

0.1

0.2

N/A

N/A

inches

 

 

 

 

 

 

W3

1.125

1.725

N/A

N/A

inches

 

 

 

 

 

 

Design Guide

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Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documentation About This DocumentTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageName Description Signal Pin DescriptionsSerial ATA Signals Pin Descriptions PCI-X Bus Pin Descriptions Sheet 1 Jtag Pin Descriptions Configuration Pin DescriptionsPCI-X Bus Pin Descriptions Sheet 2 Serial ROM Interface Pin Descriptions Power Supply Pin Descriptions1 VA0, VA1 Vccpll Pin Requirements Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingExample 1. Two-by-two Differential Impedance Matrix Trace ImpedanceDifferential Impedance Intel 31244 PCI-X to Serial ATA Controller Jtag Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsSerial ROM Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPANormal Voltage Mode Extended Voltage ModeLED LED0 LED1 LED InterfaceSDO LED SDI SCS# Sclk SCK Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Motherboard Stackup, Microstrip Motherboard Stackup for Backplane DesignsMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Stripline Stackup Backplane Stripline StackupBackplane Stripline Stackup Cable Interconnect With Backplane Cable SpecificationBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI/X Voltage Levels PCI-X Layout GuidelinesPCI Voltage Levels GND PCI/X Clocking ModesPCI-X Clocking Modes Add-on Card Routing Parameters PCI General Layout GuidelinesMinimum Maximum CLKPCI-X Slot Guidelines PCI-X Layout Guidelines For Slot ConfigurationsProtection Circuitry for Add-in Cards PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Signal Definitions Cables and ConnectorsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Parameter Min Max Test MethodologyInterface Timing and SI Requirements Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelPull-up or Pull-down Comments Terminations Pull-down/Pull-upsTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Logic Analyzer Pod 1 Sheet 1 Debug Connectors and Logic Analyzer Connectivity13Probing PCI-X Signals Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Lead H-PBGA Package Thermal Characteristics Thermal SolutionsThermal Recommendations Thermal ResistanceThis page left intentionally blank Related Documents ReferencesDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank