Intel 31244 PCI-X manual Pci-X, Fifo

Page 14

Intel® 31244 PCI-X to Serial ATA Controller

Overview

Feature Highlights:

•Four SATA Channels at 1.5 Gbits/s

•Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e Compliant

•64-bit/133 MHz PCI-X Bus. Backwards compatible to 32-bit/33 MHz and 64-bit/66 MHz

•Compatible with existing Operating Systems

•Supports native PCI IDE

•Hot-Plug Drives

•Supports Master/Slave Mode for Compatibility with existing Operating Systems

•Supports SATA Direct Port Access (Master/Master Mode)

•Independent DMA Masters for each SATA Channel

•3.3 V and 2.5 V Supply, 2 W maximum

Figure 1. Intel® 31244 PCI-X to Serial ATA Controller Block Diagram

 

 

LED0

 

 

 

P_AD(63:0)

 

LED1

 

 

 

 

LED2

 

 

 

P_CBE(7:0)

 

 

 

 

 

LED3

 

 

 

 

 

 

 

 

P_PAR

 

 

 

Serializer

TX0P

P_PAR64

 

 

Serial ATA

 

 

TX0N

 

 

PHY

P_FRAME#

 

 

Transport/Link

00B

 

 

I/F

 

 

Layer

RX0N

P_TRDY#

PCI-X

Dual

Deserializer

 

RX0P

P_IRDY#

64-bit

Port

 

 

 

 

TX1P

P_STOP#

133 MHz

FIFO

Serial ATA

Serializer

TX1N

P_DEVSEL#

Interface

and

PHY

Transport/Link

00B

 

I/O

I/F

P_REQ#

 

Layer

Deserializer

RX1N

P_REQ64#

 

Transport

 

RX1P

 

 

 

P_ACK64#

 

Engine

 

Serializer

TX2P

 

 

Serial ATA

P_GNT#

 

 

TX2N

 

 

PHY

P_CLK

 

 

Transport/Link

I/F

00B

 

 

Layer

RX2N

P_RST#

 

 

Deserializer

 

 

 

RX2P

P_PERR#

 

 

 

 

TX3P

P_SERR#

 

 

Serial ATA

Serializer

 

 

TX3N

P_INTA#

 

 

PHY

 

 

Transport/Link

00B

 

 

I/F

 

 

 

Layer

RX3N

 

 

 

Deserializer

 

 

 

 

RX3P

 

 

 

 

 

 

 

 

 

 

A9194-03

14

Design Guide

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Contents Intel 31244 PCI-X to Serial ATA Controller Design GuideIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Wire Lengths For Multiple PCI-X Load Embedded TablesRevision History Date Revision # DescriptionThis page intentionally left blank Terminology and Definitions About This DocumentReference Documentation Reference DocumentsTerminology and Definition Sheet 2 Terminology and Definition Sheet 3 ISIThis page left intentionally blank Features OverviewPCI-X FifoApplications Quad Serial ATA Host Bus AdapterThis page left intentionally blank Intel 31244 PCI-X to Serial ATA Controller Package Packaging ConsiderationsName Description Signal Pin DescriptionsSerial ATA Signals Pin Descriptions PCI-X Bus Pin Descriptions Sheet 1 Jtag Pin Descriptions Configuration Pin DescriptionsPCI-X Bus Pin Descriptions Sheet 2 Serial ROM Interface Pin Descriptions Power Supply Pin Descriptions1 VA0, VA1 Vccpll Pin Requirements Package/Marking Information Package Information 256-pin PbgaBall Map By Function Pbga Mapped By Pin FunctionThis page left intentionally blank Routing Guidelines General Routing GuidelinesCrosstalk Crosstalk Effects on Trace Distance and HeightEMI Considerations Power Distribution and Decoupling DecouplingExample 1. Two-by-two Differential Impedance Matrix Trace ImpedanceDifferential Impedance Intel 31244 PCI-X to Serial ATA Controller Jtag Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsSerial ROM Interface PCI-X Interface Normal Voltage Mode Direct Port Access DPAExtended Voltage Mode Extended Voltage ModeLED LED0 LED1 LED InterfaceSDO LED SDI SCS# Sclk SCK Reference Clock Generation Load Capacitance 20 pF Shunt Capacitance 7 pFThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Extended Voltage Mode Intel 31244 PCI-X to Serial ATA Controller HBA StackupBackplane Topologies Write Backplane TopologyRead Backplane Topology Motherboard Microstrip Parameters Motherboard Stackup for Backplane DesignsMotherboard Stackup, Microstrip Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Stripline Stackup Backplane Stripline StackupBackplane Stripline Stackup Backplane Stackup, Microstrip Cable SpecificationCable Interconnect With Backplane Backplane Stackup, Offset StriplineThis page left intentionally blank PCI/X Voltage Levels PCI-X Layout GuidelinesPCI Voltage Levels GND PCI/X Clocking ModesPCI-X Clocking Modes Minimum Maximum PCI General Layout GuidelinesAdd-on Card Routing Parameters CLKPCI-X Slot Guidelines PCI-X Layout Guidelines For Slot ConfigurationsProtection Circuitry for Add-in Cards PCI Clock Layout Guidelines Wiring Lengths for Single Slot Segment Lower AD Bus Upper AD BusLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Cabling Cables and ConnectorsSerial ATA Signal Definitions Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Signal Connections Serial ATA CableVoltage Power Delivery This page left intentionally blank Parameter Min Max Test MethodologyInterface Timing and SI Requirements Serial ATA Eye Diagram Timing RequirementExtended Voltage Mode Receiver Model Extended Voltage Mode ReceiverExtended Voltage Mode Driver Model Extended Mode DriverPull-up or Pull-down Comments Terminations Pull-down/Pull-upsTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Logic Analyzer Pod 1 Sheet 1 Debug Connectors and Logic Analyzer Connectivity13Probing PCI-X Signals Logic Analyzer Pod 1 Sheet 2 Logic Analyzer PodIrdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Recommendations Thermal SolutionsLead H-PBGA Package Thermal Characteristics Thermal ResistanceThis page left intentionally blank Design References ReferencesRelated Documents Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank
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