Intel 31244 PCI-X manual Figures

Page 5

 

Intel® 31244 PCI-X to Serial ATA Controller

 

 

Contents

Figures

 

1

Intel® 31244 PCI-X to Serial ATA Controller Block Diagram

14

2

Quad Serial ATA Host Bus Adapter

15

3

Packaging Considerations

17

4

Package Information: 256-pin PBGA

22

5

PBGA Mapped By Pin Function

23

6

Examples of Stubless and Short Stub Traces

25

7

Crosstalk Effects on Trace Distance and Height

26

8

PCB Ground Layout Around Connectors

26

9

Cross Section of Differential Trace

29

10

LED and Serial EEPROM Configurations

34

11

Intel® 31244 PCI-X to Serial ATA Controller Connection Scheme - Normal Mode

38

12

Intel® 31244 PCI-X to Serial ATA Controller HBA Stackup

39

13

Write Backplane Topology

40

14

Read Backplane Topology

41

15

Microstrip Stackup

43

16

Stripline Stackup

44

17

Single-Slot Topology

52

18

Embedded Intel® 31244 PCI-X to Serial ATA Controller

 

 

Design with Single PCI-X Load

53

19

Embedded PCI-X Design With Multiple Loads

54

20

Serial ATA Direct Connect

55

21

Serial ATA Connectors Cable to Host Connections

56

22

Serial ATA Host Connectors

57

23

Serial ATA Cable Signal Connections

58

24

Serial ATA Eye Diagram

62

25

Extended Mode Receiver Example

63

26

Extended Mode Driver Example

64

27

Intel® IQ31244 PCI-X to Serial ATA Controller Evaluation Platform Board

 

 

Block Diagram

67

Design Guide

5

Image 5
Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documentation About This DocumentTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageName Description Signal Pin DescriptionsSerial ATA Signals Pin Descriptions PCI-X Bus Pin Descriptions Sheet 1 Jtag Pin Descriptions Configuration Pin DescriptionsPCI-X Bus Pin Descriptions Sheet 2 Serial ROM Interface Pin Descriptions Power Supply Pin Descriptions1 VA0, VA1 Vccpll Pin Requirements Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingExample 1. Two-by-two Differential Impedance Matrix Trace ImpedanceDifferential Impedance Intel 31244 PCI-X to Serial ATA Controller Jtag Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsSerial ROM Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPANormal Voltage Mode Extended Voltage ModeLED LED0 LED1 LED InterfaceSDO LED SDI SCS# Sclk SCK Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Motherboard Stackup, Microstrip Motherboard Stackup for Backplane DesignsMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Stripline Stackup Backplane Stripline StackupBackplane Stripline Stackup Cable Interconnect With Backplane Cable SpecificationBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI/X Voltage Levels PCI-X Layout GuidelinesPCI Voltage Levels GND PCI/X Clocking ModesPCI-X Clocking Modes Add-on Card Routing Parameters PCI General Layout GuidelinesMinimum Maximum CLKPCI-X Slot Guidelines PCI-X Layout Guidelines For Slot ConfigurationsProtection Circuitry for Add-in Cards PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Signal Definitions Cables and ConnectorsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Parameter Min Max Test MethodologyInterface Timing and SI Requirements Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelPull-up or Pull-down Comments Terminations Pull-down/Pull-upsTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Logic Analyzer Pod 1 Sheet 1 Debug Connectors and Logic Analyzer Connectivity13Probing PCI-X Signals Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Lead H-PBGA Package Thermal Characteristics Thermal SolutionsThermal Recommendations Thermal ResistanceThis page left intentionally blank Related Documents ReferencesDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank