Intel 31244 PCI-X manual Cable Interconnect With Backplane, Backplane Stackup, Microstrip

Page 45

Intel® 31244 PCI-X to Serial ATA Controller

Printed Circuit Board (PCB) Methodology

Table 15.

Backplane Stackup, Microstrip

 

 

 

 

 

 

 

 

 

 

Variable

Nominal (mil)

Tolerance

Min (mil)

Max (mil)

 

 

 

 

 

 

 

Mask Thickness

0.8

+/- 0.2

0.6

1.0

 

 

 

 

 

 

 

Mask Er

3.6

 

3.6

3.6

 

 

 

 

 

 

 

Trace Height

1.4

+/-0.3

1.1

1.7

 

 

 

 

 

 

 

Preg Er

4.66

+/-0.55

3.6

4.7

 

 

 

 

 

 

 

Plane Thickness

1.4

+/-0.2

1.2

1.6

 

 

 

 

 

 

 

Trace Thickness

1.4

+/-0.4

1.0

1.8

 

 

 

 

 

 

 

Trace Width

11.5

+/-1.5

10

13

 

 

 

 

 

 

 

Total Thickness

70.0

+/-7.0

63.0

77.0

 

 

 

 

 

 

Table 16.

Backplane Stackup, Offset Stripline

 

 

 

 

 

 

 

 

 

 

 

Variable

Nominal (mil)

 

Tolerance

Min (mil)

Max (mil)

 

 

 

 

 

 

 

 

Mask Thickness

0.8

 

+/- 0.2

0.6

1.0

 

 

 

 

 

 

 

 

Mask Er

3.6

 

 

3.6

3.6

 

 

 

 

 

 

 

 

Trace Height

1

 

+/-0.3

 

 

 

 

 

 

 

 

 

 

Preg Er

4.15

 

+/-0.55

3.6

4.7

 

 

 

 

 

 

 

 

Plane Thickness

2.2

 

+/-0.2

1.2

1.6

 

 

 

 

 

 

 

 

Trace Thickness

1.4

 

+/-0.4

1.8

2.6

 

 

 

 

 

 

 

 

Trace Width

11.5

 

+/-1.5

 

 

 

 

 

 

 

 

 

 

Total Thickness

70.0

 

+/-7.0

63.0

77.0

 

 

 

 

 

 

 

6.2.4Cable Interconnect With Backplane

Figure 14 provides the topology which uses a cable as an interconnect between the motherboard and backplane.

Table 17.

Cable Specification

 

 

 

 

 

 

 

Parameter

Routing Guideline

Notes

 

 

 

 

 

Characteristic Z - Cable

100 ohms +/- 15%

 

 

 

 

 

 

Trace Length

1”-6”

 

 

 

 

 

 

Trace Matching

150 mils

 

 

 

 

 

Design Guide

45

Image 45
Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documentation About This DocumentTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageSignal Pin Descriptions Serial ATA Signals Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 Configuration Pin Descriptions PCI-X Bus Pin Descriptions Sheet 2Jtag Pin Descriptions Power Supply Pin Descriptions 1 VA0, VA1 Vccpll Pin RequirementsSerial ROM Interface Pin Descriptions Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingTrace Impedance Differential ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Intel 31244 PCI-X to Serial ATA Controller Interface Ports Serial ROM InterfaceJtag Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPANormal Voltage Mode Extended Voltage ModeLED Interface SDO LED SDI SCS# Sclk SCKLED LED0 LED1 Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Motherboard Stackup, Microstrip Motherboard Stackup for Backplane DesignsMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Cable Interconnect With Backplane Cable SpecificationBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI-X Layout Guidelines PCI Voltage LevelsPCI/X Voltage Levels PCI/X Clocking Modes PCI-X Clocking ModesGND Add-on Card Routing Parameters PCI General Layout GuidelinesMinimum Maximum CLKPCI-X Layout Guidelines For Slot Configurations Protection Circuitry for Add-in CardsPCI-X Slot Guidelines PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Signal Definitions Cables and ConnectorsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Test Methodology Interface Timing and SI RequirementsParameter Min Max Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelTerminations Pull-down/Pull-ups Terminations Pull-up/Pull-down Sheet 1Pull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Debug Connectors and Logic Analyzer Connectivity13 Probing PCI-X SignalsLogic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Lead H-PBGA Package Thermal Characteristics Thermal SolutionsThermal Recommendations Thermal ResistanceThis page left intentionally blank Related Documents ReferencesDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank