Intel 31244 PCI-X manual Reference Clock Generation, Load Capacitance 20 pF Shunt Capacitance 7 pF

Page 35

5.4.4Reference Clock Generation

A 37.5 MHz reference clock with a +/- 100 ppm accuracy is required for proper operation of the GD31244. This is generated from an external oscillator connected directly to the XI input. Optionally, a 37.5 MHz crystal may be connected between the XI and XO pins with a 20 pF capacitor from XI to ground and another from XO to ground. The following are the crystal characteristics:

Frequency: 37.5 MHz +/- 100 ppm

Mode: Fundamental

Type: Parallel resonant

ESR: 30 Ohms maximum

Load Capacitance: 20 pF

Shunt Capacitance: 7 pF

Drive Level: 500 mW maximum

Recommended Vendor/Part Number: Fox Electronics, Part number: 278-37.5-8 (This is an HC-49SD surface mountable package.)

Place the crystal near the GD31244 and isolated from noisy circuits as much as possible.

Design Guide

35

Image 35
Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documents About This DocumentReference Documentation Terminology and DefinitionsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageName Description Signal Pin DescriptionsSerial ATA Signals Pin Descriptions PCI-X Bus Pin Descriptions Sheet 1 Jtag Pin Descriptions Configuration Pin DescriptionsPCI-X Bus Pin Descriptions Sheet 2 Serial ROM Interface Pin Descriptions Power Supply Pin Descriptions1 VA0, VA1 Vccpll Pin Requirements Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingExample 1. Two-by-two Differential Impedance Matrix Trace ImpedanceDifferential Impedance Intel 31244 PCI-X to Serial ATA Controller Jtag Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsSerial ROM Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPAExtended Voltage Mode Normal Voltage ModeLED LED0 LED1 LED InterfaceSDO LED SDI SCS# Sclk SCK Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Variable Nominal mil Tolerance Min mil Max mil Motherboard Stackup for Backplane DesignsMotherboard Stackup, Microstrip Motherboard Microstrip ParametersMicrostrip Stackup Stripline Stackup Backplane Stripline StackupBackplane Stripline Stackup Backplane Stackup, Offset Stripline Cable SpecificationCable Interconnect With Backplane Backplane Stackup, MicrostripThis page left intentionally blank PCI/X Voltage Levels PCI-X Layout GuidelinesPCI Voltage Levels GND PCI/X Clocking ModesPCI-X Clocking Modes CLK PCI General Layout GuidelinesAdd-on Card Routing Parameters Minimum MaximumPCI-X Slot Guidelines PCI-X Layout Guidelines For Slot ConfigurationsProtection Circuitry for Add-in Cards PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Direct Connect Cables and ConnectorsSerial ATA Signal Definitions CablingCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Parameter Min Max Test MethodologyInterface Timing and SI Requirements Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelPull-up or Pull-down Comments Terminations Pull-down/Pull-upsTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Logic Analyzer Pod 1 Sheet 1 Debug Connectors and Logic Analyzer Connectivity13Probing PCI-X Signals Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Resistance Thermal SolutionsLead H-PBGA Package Thermal Characteristics Thermal RecommendationsThis page left intentionally blank Design References ReferencesRelated Documents Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank