Intel 31244 PCI-X manual Conn

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Intel® 31244 PCI-X to Serial ATA Controller

Printed Circuit Board (PCB) Methodology

6.1Intel® 31244 PCI-X to Serial ATA Controller Normal Mode (standard SATA driver)

This section provides recommendations for the GD31244 running in the standard SATA mode. Figure 11 shows a standard SATA setup with the GD31244 connected to trace on the motherboard. This trace terminates with a connector. The SATA cable connects to the SATA motherboard cable with the other end connecting to connector on the hard drive. The traces from the SATA hard drive connector connect to the SATA interface IC on the hard drive.

Figure 11. Intel® 31244 PCI-X to Serial ATA Controller Connection Scheme - Normal Mode

Intel®

31244

MB

Traces

Conn.

Cable

Conn.

HD

Traces

SATA IC

B0423-02

Table 11.

Normal Voltage Mode

 

 

 

 

 

Parameter

Routing Guideline

 

 

 

 

Single Ended Trace Impedance

Microstrip stackup

 

 

 

 

Reference Plane

ground

 

 

 

 

Impedance

100 ohms differential impedance

 

 

 

 

Trace Thickness

1.4 mil

 

 

 

 

Trace Width

5 mil

 

 

 

 

Intra Pair Trace Spacing

7 mil

 

 

 

 

Pair to Pair

20 mil minimum

 

Trace Spacing

 

 

 

 

 

 

Trace Length

2” to 5”

 

 

 

 

Trace Length Matching

100 mils

 

 

 

 

Cable Length

1 meter

 

 

 

 

Hard drive PCB Length from connector to SATA

1”

 

interface IC.

 

 

 

 

 

 

Vias

Minimize number of vias (none preferred). Each

 

channel in the pair has an equal number of vias.

 

 

 

 

 

38

Design Guide

Image 38
Contents Intel 31244 PCI-X to Serial ATA Controller Design GuideIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Wire Lengths For Multiple PCI-X Load Embedded TablesRevision History Date Revision # DescriptionThis page intentionally left blank Terminology and Definitions About This DocumentReference Documentation Reference DocumentsTerminology and Definition Sheet 2 Terminology and Definition Sheet 3 ISIThis page left intentionally blank Features OverviewPCI-X FifoApplications Quad Serial ATA Host Bus AdapterThis page left intentionally blank Intel 31244 PCI-X to Serial ATA Controller Package Packaging ConsiderationsName Description Signal Pin DescriptionsSerial ATA Signals Pin Descriptions PCI-X Bus Pin Descriptions Sheet 1 Jtag Pin Descriptions Configuration Pin DescriptionsPCI-X Bus Pin Descriptions Sheet 2 Serial ROM Interface Pin Descriptions Power Supply Pin Descriptions1 VA0, VA1 Vccpll Pin Requirements Package/Marking Information Package Information 256-pin PbgaBall Map By Function Pbga Mapped By Pin FunctionThis page left intentionally blank Routing Guidelines General Routing GuidelinesCrosstalk Crosstalk Effects on Trace Distance and HeightEMI Considerations Power Distribution and Decoupling DecouplingExample 1. Two-by-two Differential Impedance Matrix Trace ImpedanceDifferential Impedance Intel 31244 PCI-X to Serial ATA Controller Jtag Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsSerial ROM Interface PCI-X Interface Normal Voltage Mode Direct Port Access DPAExtended Voltage Mode Extended Voltage ModeLED LED0 LED1 LED InterfaceSDO LED SDI SCS# Sclk SCK Reference Clock Generation Load Capacitance 20 pF Shunt Capacitance 7 pFThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Extended Voltage Mode Intel 31244 PCI-X to Serial ATA Controller HBA StackupBackplane Topologies Write Backplane TopologyRead Backplane Topology Motherboard Microstrip Parameters Motherboard Stackup for Backplane DesignsMotherboard Stackup, Microstrip Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Stripline Stackup Backplane Stripline StackupBackplane Stripline Stackup Backplane Stackup, Microstrip Cable SpecificationCable Interconnect With Backplane Backplane Stackup, Offset StriplineThis page left intentionally blank PCI/X Voltage Levels PCI-X Layout GuidelinesPCI Voltage Levels GND PCI/X Clocking ModesPCI-X Clocking Modes Minimum Maximum PCI General Layout GuidelinesAdd-on Card Routing Parameters CLKPCI-X Slot Guidelines PCI-X Layout Guidelines For Slot ConfigurationsProtection Circuitry for Add-in Cards PCI Clock Layout Guidelines Wiring Lengths for Single Slot Segment Lower AD Bus Upper AD BusLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Cabling Cables and ConnectorsSerial ATA Signal Definitions Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Signal Connections Serial ATA CableVoltage Power Delivery This page left intentionally blank Parameter Min Max Test MethodologyInterface Timing and SI Requirements Serial ATA Eye Diagram Timing RequirementExtended Voltage Mode Receiver Model Extended Voltage Mode ReceiverExtended Voltage Mode Driver Model Extended Mode DriverPull-up or Pull-down Comments Terminations Pull-down/Pull-upsTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Logic Analyzer Pod 1 Sheet 1 Debug Connectors and Logic Analyzer Connectivity13Probing PCI-X Signals Logic Analyzer Pod 1 Sheet 2 Logic Analyzer PodIrdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Recommendations Thermal SolutionsLead H-PBGA Package Thermal Characteristics Thermal ResistanceThis page left intentionally blank Design References ReferencesRelated Documents Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank