Intel 31244 PCI-X manual PCI-X Signal Name

Page 72

Intel® 31244 PCI-X to Serial ATA Controller

Debug Connectors and Logic Analyzer Connectivity

Table 34.

Logic Analyzer Pod 4

 

 

 

 

 

 

 

Mictor-38 #2 Pin Number Odd Pod

Logic Analyzer Channel Number

PCI-X Signal Name

 

 

 

 

 

5

CLK/16

UNUSED

 

 

 

 

 

7

15

AD31

 

 

 

 

 

9

14

AD30

 

 

 

 

 

11

13

AD29

 

 

 

 

 

13

12

AD28

 

 

 

 

 

15

11

AD27

 

 

 

 

 

17

10

AD26

 

 

 

 

 

19

9

AD25

 

 

 

 

 

21

8

AD24

 

 

 

 

 

23

7

AD23

 

 

 

 

 

25

6

AD22

 

 

 

 

 

27

5

AD21

 

 

 

 

 

29

4

AD20

 

 

 

 

 

31

3

AD19

 

 

 

 

 

33

2

AD18

 

 

 

 

 

35

1

AD17

 

 

 

 

 

37

0

AD16

 

 

 

 

Table 35.

Logic Analyzer Pod 5

 

 

 

 

 

 

 

Mictor-38 #3 Pin Number Odd Pod

Logic Analyzer Channel Number

PCI-X Signal Name

 

 

 

 

 

6

CLK/16

PAR64

 

 

 

 

 

8

15

AD47

 

 

 

 

 

10

14

AD46

 

 

 

 

 

12

13

AD45

 

 

 

 

 

14

12

AD44

 

 

 

 

 

16

11

AD43

 

 

 

 

 

18

10

AD42

 

 

 

 

 

20

9

AD41

 

 

 

 

 

22

8

AD40

 

 

 

 

 

24

7

AD39

 

 

 

 

 

26

6

AD38

 

 

 

 

 

28

5

AD37

 

 

 

 

 

30

4

AD36

 

 

 

 

 

32

3

AD35

 

 

 

 

 

34

2

AD34

 

 

 

 

 

36

1

AD33

 

 

 

 

 

38

0

AD32

 

 

 

 

72

Design Guide

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Image 72
Page 71 Page 73
Contents Intel 31244 PCI-X to Serial ATA Controller Design GuideIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Wire Lengths For Multiple PCI-X Load Embedded TablesRevision History Date Revision # DescriptionThis page intentionally left blank About This Document Reference DocumentationTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 Terminology and Definition Sheet 3 ISIThis page left intentionally blank Features OverviewPCI-X FifoApplications Quad Serial ATA Host Bus AdapterThis page left intentionally blank Intel 31244 PCI-X to Serial ATA Controller Package Packaging ConsiderationsSignal Pin Descriptions Serial ATA Signals Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 Configuration Pin Descriptions PCI-X Bus Pin Descriptions Sheet 2Jtag Pin Descriptions Power Supply Pin Descriptions 1 VA0, VA1 Vccpll Pin RequirementsSerial ROM Interface Pin Descriptions Package/Marking Information Package Information 256-pin PbgaBall Map By Function Pbga Mapped By Pin FunctionThis page left intentionally blank Routing Guidelines General Routing GuidelinesCrosstalk Crosstalk Effects on Trace Distance and HeightEMI Considerations Power Distribution and Decoupling DecouplingTrace Impedance Differential ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Intel 31244 PCI-X to Serial ATA Controller Interface Ports Serial ROM InterfaceJtag Interface PCI-X Interface Direct Port Access DPA Extended Voltage ModeNormal Voltage Mode Extended Voltage ModeLED Interface SDO LED SDI SCS# Sclk SCKLED LED0 LED1 Reference Clock Generation Load Capacitance 20 pF Shunt Capacitance 7 pFThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Extended Voltage Mode Intel 31244 PCI-X to Serial ATA Controller HBA StackupBackplane Topologies Write Backplane TopologyRead Backplane Topology Motherboard Stackup for Backplane Designs Motherboard Stackup, MicrostripMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Cable Specification Cable Interconnect With BackplaneBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI-X Layout Guidelines PCI Voltage LevelsPCI/X Voltage Levels PCI/X Clocking Modes PCI-X Clocking ModesGND PCI General Layout Guidelines Add-on Card Routing ParametersMinimum Maximum CLKPCI-X Layout Guidelines For Slot Configurations Protection Circuitry for Add-in CardsPCI-X Slot Guidelines PCI Clock Layout Guidelines Wiring Lengths for Single Slot Segment Lower AD Bus Upper AD BusLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Cables and Connectors Serial ATA Signal DefinitionsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Signal Connections Serial ATA CableVoltage Power Delivery This page left intentionally blank Test Methodology Interface Timing and SI RequirementsParameter Min Max Serial ATA Eye Diagram Timing RequirementExtended Voltage Mode Receiver Model Extended Voltage Mode ReceiverExtended Voltage Mode Driver Model Extended Mode DriverTerminations Pull-down/Pull-ups Terminations Pull-up/Pull-down Sheet 1Pull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Debug Connectors and Logic Analyzer Connectivity13 Probing PCI-X SignalsLogic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod 1 Sheet 2 Logic Analyzer PodIrdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Solutions Lead H-PBGA Package Thermal CharacteristicsThermal Recommendations Thermal ResistanceThis page left intentionally blank References Related DocumentsDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank
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