Intel 31244 PCI-X manual Tables, Wire Lengths For Multiple PCI-X Load Embedded

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Intel® 31244 PCI-X to Serial ATA Controller

Contents

Tables

 

1

Reference Documents

9

2

Terminology and Definition

9

3

Serial ATA Signals Pin Descriptions

18

4

PCI-X Bus Pin Descriptions

19

5

Configuration Pin Descriptions

20

6

JTAG Pin Descriptions

20

7

Serial ROM Interface Pin Descriptions

21

8

Power Supply Pin Descriptions

21

9

Normal Voltage Mode

33

10

Extended Voltage Mode

33

11

Normal Voltage Mode

38

12

Motherboard Stackup, Microstrip

42

13

Motherboard Microstrip Parameters

42

14

Backplane Stripline Stackup

44

16

Backplane Stackup, Offset Stripline

45

15

Backplane Stackup, Microstrip

45

17

Cable Specification

45

18

PCI/X Voltage Levels

47

19

PCI-X Clocking Modes

48

20

Add-on Card Routing Parameters

49

21

PCI-X Slot Guidelines

50

22

Wiring Lengths for Single Slot

52

23

Wiring Lengths for Embedded Intel® 31244 PCI-X to Serial ATA Controller

 

 

with Single PCI-X Load

53

24

Wire Lengths For Multiple PCI-X Load Embedded

 

 

Intel® 31244 PCI-X to Serial ATA Controller Design

54

25

Serial ATA Signal Definitions

55

26

Interface Timing and SI Requirements

61

27

Timing Requirement

62

28

Extended Voltage Mode Receiver

63

29

Extended Mode Driver

64

30

Terminations: Pull-up/Pull-down

65

31

Logic Analyzer Pod 1

69

32

Logic Analyzer Pod 2

70

33

Logic Analyzer Pod 3

71

35

Logic Analyzer Pod 5

72

34

Logic Analyzer Pod 4

72

36

Logic Analyzer Pod 6

73

37

Thermal Resistance

77

38

544-LeadH-PBGA Package Thermal Characteristics

77

39

Design References

79

40

Intel Related Documentation

79

41

Electronic Information

80

6

Design Guide

Image 6
Contents Intel 31244 PCI-X to Serial ATA Controller Design GuideIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Wire Lengths For Multiple PCI-X Load Embedded TablesRevision History Date Revision # DescriptionThis page intentionally left blank Terminology and Definitions About This DocumentReference Documentation Reference DocumentsTerminology and Definition Sheet 2 Terminology and Definition Sheet 3 ISIThis page left intentionally blank Features OverviewPCI-X FifoApplications Quad Serial ATA Host Bus AdapterThis page left intentionally blank Intel 31244 PCI-X to Serial ATA Controller Package Packaging ConsiderationsSignal Pin Descriptions Serial ATA Signals Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 Configuration Pin Descriptions PCI-X Bus Pin Descriptions Sheet 2Jtag Pin Descriptions Power Supply Pin Descriptions 1 VA0, VA1 Vccpll Pin RequirementsSerial ROM Interface Pin Descriptions Package/Marking Information Package Information 256-pin PbgaBall Map By Function Pbga Mapped By Pin FunctionThis page left intentionally blank Routing Guidelines General Routing GuidelinesCrosstalk Crosstalk Effects on Trace Distance and HeightEMI Considerations Power Distribution and Decoupling DecouplingTrace Impedance Differential ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Intel 31244 PCI-X to Serial ATA Controller Interface Ports Serial ROM InterfaceJtag Interface PCI-X Interface Normal Voltage Mode Direct Port Access DPAExtended Voltage Mode Extended Voltage ModeLED Interface SDO LED SDI SCS# Sclk SCKLED LED0 LED1 Reference Clock Generation Load Capacitance 20 pF Shunt Capacitance 7 pFThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Extended Voltage Mode Intel 31244 PCI-X to Serial ATA Controller HBA StackupBackplane Topologies Write Backplane TopologyRead Backplane Topology Motherboard Microstrip Parameters Motherboard Stackup for Backplane DesignsMotherboard Stackup, Microstrip Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Backplane Stackup, Microstrip Cable SpecificationCable Interconnect With Backplane Backplane Stackup, Offset StriplineThis page left intentionally blank PCI-X Layout Guidelines PCI Voltage LevelsPCI/X Voltage Levels PCI/X Clocking Modes PCI-X Clocking ModesGND Minimum Maximum PCI General Layout GuidelinesAdd-on Card Routing Parameters CLKPCI-X Layout Guidelines For Slot Configurations Protection Circuitry for Add-in CardsPCI-X Slot Guidelines PCI Clock Layout Guidelines Wiring Lengths for Single Slot Segment Lower AD Bus Upper AD BusLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Cabling Cables and ConnectorsSerial ATA Signal Definitions Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Signal Connections Serial ATA CableVoltage Power Delivery This page left intentionally blank Test Methodology Interface Timing and SI RequirementsParameter Min Max Serial ATA Eye Diagram Timing RequirementExtended Voltage Mode Receiver Model Extended Voltage Mode ReceiverExtended Voltage Mode Driver Model Extended Mode DriverTerminations Pull-down/Pull-ups Terminations Pull-up/Pull-down Sheet 1Pull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Debug Connectors and Logic Analyzer Connectivity13 Probing PCI-X SignalsLogic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod 1 Sheet 2 Logic Analyzer PodIrdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Recommendations Thermal SolutionsLead H-PBGA Package Thermal Characteristics Thermal ResistanceThis page left intentionally blank Design References ReferencesRelated Documents Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank