Intel manual Intel 31244 PCI-X to Serial ATA Controller Interface Ports, Serial ROM Interface

Intel® 31244 PCI-X to Serial ATA Controller

Intel® 31244 PCI-X to Serial ATA Controller Interface Ports

Intel® 31244 PCI-X to Serial ATA	5
Controller Interface Ports

5.1Serial ROM Interface

In add-in card applications, firmware may be downloaded to the system from a Serial EEPROM or Serial Flash ROM, through the Serial ROM Interface. This industry standard, 4-pin interface, allows any size of device, up to 128 Kbytes, to be connected to the Intel® GD31244 PCI-X to serial ATA controller. This SPI interface was designed for compatibility with an ST Microelectronics* M25P10-A or Atmel* AT25F1024 device. Two of the pins are dual purpose to support four LED port activity indicators. This four pin interface is defined as follows:

1.SDI INPUT: Connects to the serial data output (SO) of the Serial EEPROM. Data is shifted out of the EEPROM on the falling edge of SCLK. Customers are recommended to add pads for both a pull-up and a pull-down resistor for possible use in the future.

2.SDO OUTPUT: Connects to the serial data input (SI) of the Serial EEPROM. Data is latched into the Serial EEPROM on the rising edge of SCLK. This is also the activity LED output for Channel 3 when all four LEDs are activated (active LOW).

3.SCLK OUTPUT: Connects to the clock input (SCK) of the Serial EEPROM. This is also the activity LED output for Channel 2 when all four LEDs are activated (active LOW).

4.SCS# OUTPUT: Connects to the chip select input (CS#) of the Serial EEPROM.

5.2JTAG Interface

An IEEE 1149.1 compatible JTAG interface and boundary scan functionality is provided to assist on-board testing of the device. A BSDL test file is provided by Intel.

Design Guide 31