Intel manual Intel 31244 PCI-X to Serial ATA Controller Interface Ports, Serial ROM Interface

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Intel® 31244 PCI-X to Serial ATA Controller

Intel® 31244 PCI-X to Serial ATA Controller Interface Ports

Intel® 31244 PCI-X to Serial ATA

5

Controller Interface Ports

5.1Serial ROM Interface

In add-in card applications, firmware may be downloaded to the system from a Serial EEPROM or Serial Flash ROM, through the Serial ROM Interface. This industry standard, 4-pin interface, allows any size of device, up to 128 Kbytes, to be connected to the Intel® GD31244 PCI-X to serial ATA controller. This SPI interface was designed for compatibility with an ST Microelectronics* M25P10-A or Atmel* AT25F1024 device. Two of the pins are dual purpose to support four LED port activity indicators. This four pin interface is defined as follows:

1.SDI INPUT: Connects to the serial data output (SO) of the Serial EEPROM. Data is shifted out of the EEPROM on the falling edge of SCLK. Customers are recommended to add pads for both a pull-up and a pull-down resistor for possible use in the future.

2.SDO OUTPUT: Connects to the serial data input (SI) of the Serial EEPROM. Data is latched into the Serial EEPROM on the rising edge of SCLK. This is also the activity LED output for Channel 3 when all four LEDs are activated (active LOW).

3.SCLK OUTPUT: Connects to the clock input (SCK) of the Serial EEPROM. This is also the activity LED output for Channel 2 when all four LEDs are activated (active LOW).

4.SCS# OUTPUT: Connects to the chip select input (CS#) of the Serial EEPROM.

5.2JTAG Interface

An IEEE 1149.1 compatible JTAG interface and boundary scan functionality is provided to assist on-board testing of the device. A BSDL test file is provided by Intel.

Design Guide

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Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documents About This DocumentReference Documentation Terminology and DefinitionsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageSerial ATA Signals Pin Descriptions Signal Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 PCI-X Bus Pin Descriptions Sheet 2 Configuration Pin DescriptionsJtag Pin Descriptions 1 VA0, VA1 Vccpll Pin Requirements Power Supply Pin DescriptionsSerial ROM Interface Pin Descriptions Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingDifferential Impedance Trace ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Serial ROM Interface Intel 31244 PCI-X to Serial ATA Controller Interface PortsJtag Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPAExtended Voltage Mode Normal Voltage ModeSDO LED SDI SCS# Sclk SCK LED InterfaceLED LED0 LED1 Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Variable Nominal mil Tolerance Min mil Max mil Motherboard Stackup for Backplane DesignsMotherboard Stackup, Microstrip Motherboard Microstrip ParametersMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Backplane Stackup, Offset Stripline Cable SpecificationCable Interconnect With Backplane Backplane Stackup, MicrostripThis page left intentionally blank PCI Voltage Levels PCI-X Layout GuidelinesPCI/X Voltage Levels PCI-X Clocking Modes PCI/X Clocking ModesGND CLK PCI General Layout GuidelinesAdd-on Card Routing Parameters Minimum MaximumProtection Circuitry for Add-in Cards PCI-X Layout Guidelines For Slot ConfigurationsPCI-X Slot Guidelines PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Direct Connect Cables and ConnectorsSerial ATA Signal Definitions CablingCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Interface Timing and SI Requirements Test MethodologyParameter Min Max Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelTerminations Pull-up/Pull-down Sheet 1 Terminations Pull-down/Pull-upsPull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity13Logic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Resistance Thermal SolutionsLead H-PBGA Package Thermal Characteristics Thermal RecommendationsThis page left intentionally blank Design References ReferencesRelated Documents Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank