Intel 31244 PCI-X manual Terminology and Definition Sheet 3, Isi

		Intel® 31244 PCI-X to Serial ATA Controller
		About This Document
Table 2.	Terminology and Definition (Sheet 3 of 3)
	Term	Definition
	RxData	Serially encoded 10b data attached to the high-speed serial differential line receiver.
	10b encoding	The 8B/10B encoding scheme transmits eight bits as a 10-bit code group. This encoding is
		used with Gigabit Ethernet, Fibre Channel and InfiniBand*.
	Jitter	Jitter is a high-frequency, semi-random displacement of a signal from its ideal location.
		Inter-symbol interference. Data-dependent deterministic jitter caused by the time differences
		required for the signal to arrive at the receiver threshold when starting from different places in
		bit sequences (symbols).
		For example media attenuates the peak amplitude of the bit sequence [0,1,0,1...], more than
		it attenuates the peak amplitude of the bit sequence [0,0,0,0,1,1,1,1...], thus the time required
		to reach the receiver threshold with the [0,1,0,1...] sequence is less than required from the
	ISI	[0,0,0,0,1,1,1,1...] sequence.
		The run length of 4 produces a higher amplitude which takes more time to overcome when
		changing bit values and therefore produces a time difference compared to the run length of
		1-bit sequence. When different run lengths are mixed in the same transmission the different
		bit sequences (symbols) therefore interfere with each other.
		ISI is expected whenever any bit sequence has frequency components that are propagated
		at different rates by the transmission media. This translates into high-high-frequency,
		data-dependent, jitter.
	Differential	A signal derived by taking the difference between two conductors. In this spec a differential signal
		is comprised of a positive conductor and a negative conductor. The differential signal is the
	Signal
		voltage on the positive conductor minus the voltage on the negative conductor (i.e., TX+ – TX-).

Design Guide 11