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| Intel® 31244 | |
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| Contents |
Contents |
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1 | About This Document | 9 | ||
| 1.1 | Reference Documentation | 9 | |
| 1.2 | Terminology and Definitions | 9 | |
2 | Overview | 13 | ||
| 2.1 | Features | 13 | |
| 2.2 | Applications | 15 | |
3 | Intel® 31244 | 17 | ||
| 3.1 | Signal Pin Descriptions | 18 | |
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| 3.1.1 VA0, VA1 (VCCPLL) Pin Requirements | 21 | |
| 3.2 | Package/Marking Information | 22 | |
| 3.3 | Ball Map By Function | 23 | |
4 | Routing Guidelines | 25 | ||
| 4.1 | General Routing Guidelines | 25 | |
| 4.2 | Crosstalk | 26 | |
| 4.3 | EMI Considerations | 27 | |
| 4.4 | Power Distribution and Decoupling | 28 | |
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| 4.4.1 | Decoupling | 28 |
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| 4.4.1.1 Intel® 31244 | 28 |
| 4.5 | Trace Impedance | 29 | |
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| 4.5.1 | Differential Impedance | 29 |
5 | Intel® 31244 | 31 | ||
| 5.1 | Serial ROM Interface | 31 | |
| 5.2 | JTAG Interface | 31 | |
| 5.3 | 32 | ||
| 5.4 | Serial ATA Interface | 33 | |
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| 5.4.1 | Direct Port Access (DPA) | 33 |
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| 5.4.2 | Extended Voltage Mode | 33 |
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| 5.4.3 | LED Interface | 34 |
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| 5.4.4 | Reference Clock Generation | 35 |
6 | Printed Circuit Board (PCB) Methodology | 37 |
6.1Intel® 31244
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| Normal Mode (standard SATA driver) | 38 | |
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| 6.1.1 Intel® 31244 | 39 | |
| 6.2 | Extended Voltage Mode | 39 | |
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| 6.2.1 | Backplane Topologies | 40 |
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| 6.2.2 Motherboard Stackup for Backplane Designs | 42 | |
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| 6.2.3 | Backplane Stripline Stackup | 44 |
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| 6.2.4 Cable Interconnect With Backplane | 45 | |
7 | 47 | |||
| 7.1 | PCI Voltage Levels | 47 | |
| 7.2 | PCI/X Clocking Modes | 48 |
Design Guide | 3 |