Intel 31244 PCI-X manual Contents

Page 3

 

 

 

Intel® 31244 PCI-X to Serial ATA Controller

 

 

 

 

Contents

Contents

 

 

 

 

1

About This Document

9

 

1.1

Reference Documentation

9

 

1.2

Terminology and Definitions

9

2

Overview

13

 

2.1

Features

13

 

2.2

Applications

15

3

Intel® 31244 PCI-X to Serial ATA Controller Package

17

 

3.1

Signal Pin Descriptions

18

 

 

3.1.1 VA0, VA1 (VCCPLL) Pin Requirements

21

 

3.2

Package/Marking Information

22

 

3.3

Ball Map By Function

23

4

Routing Guidelines

25

 

4.1

General Routing Guidelines

25

 

4.2

Crosstalk

26

 

4.3

EMI Considerations

27

 

4.4

Power Distribution and Decoupling

28

 

 

4.4.1

Decoupling

28

 

 

 

4.4.1.1 Intel® 31244 PCI-X to Serial ATA Controller Decoupling

28

 

4.5

Trace Impedance

29

 

 

4.5.1

Differential Impedance

29

5

Intel® 31244 PCI-X to Serial ATA Controller Interface Ports

31

 

5.1

Serial ROM Interface

31

 

5.2

JTAG Interface

31

 

5.3

PCI-X Interface

32

 

5.4

Serial ATA Interface

33

 

 

5.4.1

Direct Port Access (DPA)

33

 

 

5.4.2

Extended Voltage Mode

33

 

 

5.4.3

LED Interface

34

 

 

5.4.4

Reference Clock Generation

35

6

Printed Circuit Board (PCB) Methodology

37

6.1Intel® 31244 PCI-X to Serial ATA Controller

 

 

Normal Mode (standard SATA driver)

38

 

 

6.1.1 Intel® 31244 PCI-X to Serial ATA Controller HBA Stackup

39

 

6.2

Extended Voltage Mode

39

 

 

6.2.1

Backplane Topologies

40

 

 

6.2.2 Motherboard Stackup for Backplane Designs

42

 

 

6.2.3

Backplane Stripline Stackup

44

 

 

6.2.4 Cable Interconnect With Backplane

45

7

PCI-X Layout Guidelines

47

 

7.1

PCI Voltage Levels

47

 

7.2

PCI/X Clocking Modes

48

Design Guide

3

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Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documents About This DocumentReference Documentation Terminology and DefinitionsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageSignal Pin Descriptions Serial ATA Signals Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 Configuration Pin Descriptions PCI-X Bus Pin Descriptions Sheet 2Jtag Pin Descriptions Power Supply Pin Descriptions 1 VA0, VA1 Vccpll Pin RequirementsSerial ROM Interface Pin Descriptions Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingTrace Impedance Differential ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Intel 31244 PCI-X to Serial ATA Controller Interface Ports Serial ROM InterfaceJtag Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPAExtended Voltage Mode Normal Voltage ModeLED Interface SDO LED SDI SCS# Sclk SCKLED LED0 LED1 Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Variable Nominal mil Tolerance Min mil Max mil Motherboard Stackup for Backplane DesignsMotherboard Stackup, Microstrip Motherboard Microstrip ParametersMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Backplane Stackup, Offset Stripline Cable SpecificationCable Interconnect With Backplane Backplane Stackup, MicrostripThis page left intentionally blank PCI-X Layout Guidelines PCI Voltage LevelsPCI/X Voltage Levels PCI/X Clocking Modes PCI-X Clocking ModesGND CLK PCI General Layout GuidelinesAdd-on Card Routing Parameters Minimum MaximumPCI-X Layout Guidelines For Slot Configurations Protection Circuitry for Add-in CardsPCI-X Slot Guidelines PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Direct Connect Cables and ConnectorsSerial ATA Signal Definitions CablingCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Test Methodology Interface Timing and SI RequirementsParameter Min Max Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelTerminations Pull-down/Pull-ups Terminations Pull-up/Pull-down Sheet 1Pull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Debug Connectors and Logic Analyzer Connectivity13 Probing PCI-X SignalsLogic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Resistance Thermal SolutionsLead H-PBGA Package Thermal Characteristics Thermal RecommendationsThis page left intentionally blank Design References ReferencesRelated Documents Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank