Intel 31244 PCI-X manual Extended Voltage Mode Receiver Model

Page 63

10.1Extended Voltage Mode

Figure 25, Figure 26, Table 28 and Table 29 describe the extended voltage mode eye diagrams for the modified receiver and driver. These eye diagrams needed to be modified from the original SATA specification to allow for the higher voltage parameters required for a backplane design.

Note: The material in this section is preliminary.

10.1.1Extended Voltage Mode Receiver Model

For GD31244 reads, the GD31244 receiver must be more sensitive than the SATA specification. The extended voltage mode eye diagram for the receiver shown in Figure 25 is superimposed on the SATA specified eye pattern. Table 28 provides the same parameters in a table format. These parameters are measured at the GD31244 RX pins.

Figure 25. Extended Mode Receiver Example

Specifying a New RCV Eye for Intel® 31244 Reads

 

0.2

 

 

 

 

 

 

 

0.15

 

 

 

 

 

 

 

0.1

 

 

 

 

 

 

(V)

0.05

 

 

 

 

 

 

 

 

 

 

 

 

 

Voltage

0

 

 

 

 

 

 

0

100

200

300

400

500

600

 

 

 

 

 

 

 

 

-0.05

 

 

 

 

 

 

 

-0.1

 

 

 

 

 

 

 

-0.15

 

 

 

 

 

 

 

-0.2

 

 

 

 

 

 

Time (ps)

SATA_spec

new_ART_RCV

 

 

 

B0428-01

 

 

 

 

Table 28.

Extended Voltage Mode Receiver

 

 

 

 

 

 

Parameter

 

Value

 

 

 

 

Vdiff,rx

+/- 110 mV differential nominal. Measured at GD31244 RX pins on receive side.

 

Tjitter

0 - 7

UI maximum

 

 

 

 

 

Trise/fall (20-80%)

0.3

UI - 0.41 UI

 

 

 

 

Vmax @ backplane

600-650 mV

 

 

 

 

 

Vmin @ backplane

 

500 mV

 

 

 

 

Design Guide

63

Image 63
Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documents About This DocumentReference Documentation Terminology and DefinitionsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageSignal Pin Descriptions Serial ATA Signals Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 Configuration Pin Descriptions PCI-X Bus Pin Descriptions Sheet 2Jtag Pin Descriptions Power Supply Pin Descriptions 1 VA0, VA1 Vccpll Pin RequirementsSerial ROM Interface Pin Descriptions Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingTrace Impedance Differential ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Intel 31244 PCI-X to Serial ATA Controller Interface Ports Serial ROM InterfaceJtag Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPAExtended Voltage Mode Normal Voltage ModeLED Interface SDO LED SDI SCS# Sclk SCKLED LED0 LED1 Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Variable Nominal mil Tolerance Min mil Max mil Motherboard Stackup for Backplane DesignsMotherboard Stackup, Microstrip Motherboard Microstrip ParametersMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Backplane Stackup, Offset Stripline Cable SpecificationCable Interconnect With Backplane Backplane Stackup, MicrostripThis page left intentionally blank PCI-X Layout Guidelines PCI Voltage LevelsPCI/X Voltage Levels PCI/X Clocking Modes PCI-X Clocking ModesGND CLK PCI General Layout GuidelinesAdd-on Card Routing Parameters Minimum MaximumPCI-X Layout Guidelines For Slot Configurations Protection Circuitry for Add-in CardsPCI-X Slot Guidelines PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Direct Connect Cables and ConnectorsSerial ATA Signal Definitions CablingCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Test Methodology Interface Timing and SI RequirementsParameter Min Max Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelTerminations Pull-down/Pull-ups Terminations Pull-up/Pull-down Sheet 1Pull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Debug Connectors and Logic Analyzer Connectivity13 Probing PCI-X SignalsLogic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Thermal Resistance Thermal SolutionsLead H-PBGA Package Thermal Characteristics Thermal RecommendationsThis page left intentionally blank Design References ReferencesRelated Documents Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank