Intel 31244 PCI-X manual Debug Connectors and Logic Analyzer Connectivity13, Probing PCI-X Signals

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Intel® 31244 PCI-X to Serial ATA Controller

Debug Connectors and Logic Analyzer Connectivity

Debug Connectors and Logic Analyzer

Connectivity13

13.1Probing PCI-X Signals

To ease the probing and debug of the PCI-X signals it is recommended to passively probe the PCI-X bus signals with a logic analyzer. This may be accomplished by placing six AMP* Mictor-38 connectors on the board or probing the bus with an interposer card such as the FuturePlus Systems* FS2007 that works with an Agilent Technologies* Logic Analyzer.

For ease of debugging the pin out of the AMP Mictor-38 connectors, the recommended pin-out matches the FuturePlus Systems* configuration setup, which allow ease of viewing the PCI signals on an Agilent Technologies* Logic Analyzer. Refer to the following test equipment that is used for this analysis:

Two AMP 2-767004-2 surface mount connectors mounted on the target board and routed to the PCI-X Local bus.

Two Agilent E5346A or E5351A High-Density Adapter Cables from FuturePlus Systems or Agilent Technologies.

Four logic analyzer PODS.

FS1104 Software from FuturePlus.

The equivalent for other analyzers may be substituted. A FuturePlus Systems configuration file with the FS1104 product that matches the pinout in Table 31.

Table 31.

Logic Analyzer Pod 1 (Sheet 1 of 2)

 

 

 

 

 

 

Mictor-38 #1 Pin Number Odd Pod

Logic Analyzer Channel Number

PCI-X Name

 

 

 

 

 

6

CLKC/16

CLK

 

 

 

 

 

8

15

C/BE4

 

 

 

 

 

10

14

C/BE5

 

 

 

 

 

12

13

C/BE6

 

 

 

 

 

14

12

C/BE7

 

 

 

 

 

16

11

ACK64

 

 

 

 

 

18

10

REQ64

 

 

 

 

 

20

9

UNUSED

 

 

 

 

 

22

8

PME

 

 

 

 

 

24

7

C/BEO

 

 

 

 

 

26

6

M66EN

 

 

 

 

 

28

5

C/BE1

 

 

 

 

 

30

4

SERR

 

 

 

 

 

32

3

PAR

 

 

 

 

Design Guide

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Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documentation About This DocumentTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageSignal Pin Descriptions Serial ATA Signals Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 Configuration Pin Descriptions PCI-X Bus Pin Descriptions Sheet 2Jtag Pin Descriptions Power Supply Pin Descriptions 1 VA0, VA1 Vccpll Pin RequirementsSerial ROM Interface Pin Descriptions Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingTrace Impedance Differential ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Intel 31244 PCI-X to Serial ATA Controller Interface Ports Serial ROM InterfaceJtag Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPANormal Voltage Mode Extended Voltage ModeLED Interface SDO LED SDI SCS# Sclk SCKLED LED0 LED1 Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Motherboard Stackup, Microstrip Motherboard Stackup for Backplane DesignsMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Cable Interconnect With Backplane Cable SpecificationBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI-X Layout Guidelines PCI Voltage LevelsPCI/X Voltage Levels PCI/X Clocking Modes PCI-X Clocking ModesGND Add-on Card Routing Parameters PCI General Layout GuidelinesMinimum Maximum CLKPCI-X Layout Guidelines For Slot Configurations Protection Circuitry for Add-in CardsPCI-X Slot Guidelines PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Signal Definitions Cables and ConnectorsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Test Methodology Interface Timing and SI RequirementsParameter Min Max Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelTerminations Pull-down/Pull-ups Terminations Pull-up/Pull-down Sheet 1Pull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Debug Connectors and Logic Analyzer Connectivity13 Probing PCI-X SignalsLogic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Lead H-PBGA Package Thermal Characteristics Thermal SolutionsThermal Recommendations Thermal ResistanceThis page left intentionally blank Related Documents ReferencesDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank