Intel 31244 PCI-X manual Serial ATA Interface, Direct Port Access DPA, Extended Voltage Mode

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Intel® 31244 PCI-X to Serial ATA Controller

Intel® 31244 PCI-X to Serial ATA Controller Interface Ports

5.4Serial ATA Interface

Four 1.5 Gbits/s Serial ATA ports are located on the GD31244, to support point-to-point connectivity to disk drives, CDROMs, DVD ROMs or any other Serial ATA target device. Each port is compliant with the “Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e. High-speed differential duplex serial lines send 8B/10B encoded data to and from the GD31244 and the target at a maximum raw data rate of 1.2 Gbits/s (150 Mbytes/s). Copies of the targets Task File Registers are maintained on the GD31244 and transferred as needed to the target. The Serial ATA protocol is software compatible with all existing operating systems that support ATA devices, however, performance and reliability are improved since all data is CRC checked.

5.4.1Direct Port Access (DPA)

The SATA Direct Port Access architecture allows for independent control of the SATA devices. Unlike ATA master/slave configuration where only one drive may operate at a time, DPA allows multiple drivers to be accessed concurrently. In addition, each port supports its own DMA channel allowing each port to transfer data independently (between a device and memory).

The DPA mode does change the register layout from PCI IDE. Therefore, legacy device drivers do not support this mode. DPA requires the registers (including the Command Block, Control Block, DMA, and SATA superset) for each drive is available at all times. Instead of using I/O space, these registers are mapped to a single 4 KB block. Each port has 512 KB; the remaining 2048 KB are for the common port registers. The 4 KB block is mapped using one PCI BAR register.

5.4.2Extended Voltage Mode

The SATA voltages were designed primarily for a cable connection to the hard drives. In certain applications, such as NAS/SAN enclosures, the hard disk drives (HDD) are connected to a backplane, not a cable (typically in desktop systems). Due to the frequency of the SATA interface, the backplane creates a significant attenuation of the SATA signals. In an effort to simplify system designs, the GD31244 offers an extended voltage range to help alleviate this issue. This extended voltage range allows standard SATA HDD to be used with SATA backplanes.

The firmware may be place into the External Voltage Mode by setting bit 14 in PHY Configuration Register Address 140H to 1. This forces the firmware to operate with this extended voltage range.

Table 9.

Normal Voltage Mode

 

 

 

 

 

 

 

 

 

 

Parameter

Description

Minimum

Maximum

Units

 

 

 

 

 

 

 

VOUT

TXx output differential peak-to-peak voltage swing

400

600

mVp-p

 

VIN

RXx input differential peak-to-peak voltage swing

325

600

mVp-p

Table 10.

Extended Voltage Mode

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Description

Minimum

Maximum

Units

 

 

 

 

 

 

 

 

 

VOUT

TXx output differential peak-to-peak voltage swing

800

2000

mVp-p

 

 

∆∆VIN

RXx input differential peak-to-peak voltage swing

175

2000

mVp-p

 

Design Guide

 

 

 

 

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Contents Design Guide Intel 31244 PCI-X to Serial ATA ControllerIntel 31244 PCI-X to Serial ATA Controller Contents Connecting Intel 31244 PCI-X to Serial ATA Controller Figures Tables Wire Lengths For Multiple PCI-X Load EmbeddedDate Revision # Description Revision HistoryThis page intentionally left blank Reference Documentation About This DocumentTerminology and Definitions Reference DocumentsTerminology and Definition Sheet 2 ISI Terminology and Definition Sheet 3This page left intentionally blank Overview FeaturesFifo PCI-XQuad Serial ATA Host Bus Adapter ApplicationsThis page left intentionally blank Packaging Considerations Intel 31244 PCI-X to Serial ATA Controller PackageSignal Pin Descriptions Serial ATA Signals Pin DescriptionsName Description PCI-X Bus Pin Descriptions Sheet 1 Configuration Pin Descriptions PCI-X Bus Pin Descriptions Sheet 2Jtag Pin Descriptions Power Supply Pin Descriptions 1 VA0, VA1 Vccpll Pin RequirementsSerial ROM Interface Pin Descriptions Package Information 256-pin Pbga Package/Marking InformationPbga Mapped By Pin Function Ball Map By FunctionThis page left intentionally blank General Routing Guidelines Routing GuidelinesCrosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations Decoupling Power Distribution and DecouplingTrace Impedance Differential ImpedanceExample 1. Two-by-two Differential Impedance Matrix Intel 31244 PCI-X to Serial ATA Controller Intel 31244 PCI-X to Serial ATA Controller Interface Ports Serial ROM InterfaceJtag Interface PCI-X Interface Extended Voltage Mode Direct Port Access DPANormal Voltage Mode Extended Voltage ModeLED Interface SDO LED SDI SCS# Sclk SCKLED LED0 LED1 Load Capacitance 20 pF Shunt Capacitance 7 pF Reference Clock GenerationThis page left intentionally blank Printed Circuit Board PCB Methodology6 Conn Intel 31244 PCI-X to Serial ATA Controller HBA Stackup Extended Voltage ModeWrite Backplane Topology Backplane TopologiesRead Backplane Topology Motherboard Stackup, Microstrip Motherboard Stackup for Backplane DesignsMotherboard Microstrip Parameters Variable Nominal mil Tolerance Min mil Max milMicrostrip Stackup Backplane Stripline Stackup Backplane Stripline StackupStripline Stackup Cable Interconnect With Backplane Cable SpecificationBackplane Stackup, Microstrip Backplane Stackup, Offset StriplineThis page left intentionally blank PCI-X Layout Guidelines PCI Voltage LevelsPCI/X Voltage Levels PCI/X Clocking Modes PCI-X Clocking ModesGND Add-on Card Routing Parameters PCI General Layout GuidelinesMinimum Maximum CLKPCI-X Layout Guidelines For Slot Configurations Protection Circuitry for Add-in CardsPCI-X Slot Guidelines PCI Clock Layout Guidelines Segment Lower AD Bus Upper AD Bus Wiring Lengths for Single SlotLower AD Bus Upper AD Bus Embedded PCI-X Design With Multiple Loads Serial ATA Signal Definitions Cables and ConnectorsCabling Serial ATA Direct ConnectCables and Connectors Serial ATA Host Connectors Serial ATA Cable Serial ATA Cable Signal ConnectionsVoltage Power Delivery This page left intentionally blank Test Methodology Interface Timing and SI RequirementsParameter Min Max Timing Requirement Serial ATA Eye DiagramExtended Voltage Mode Receiver Extended Voltage Mode Receiver ModelExtended Mode Driver Extended Voltage Mode Driver ModelTerminations Pull-down/Pull-ups Terminations Pull-up/Pull-down Sheet 1Pull-up or Pull-down Comments Terminations Pull-up/Pull-down Sheet 2 Shows the block diagram of this customer reference board Features Debug Connectors and Logic Analyzer Connectivity13 Probing PCI-X SignalsLogic Analyzer Pod 1 Sheet 1 Logic Analyzer Pod Logic Analyzer Pod 1 Sheet 2Irdy PCI-X Signal Name Logic Analyzer Pod This page left intentionally blank Design for Manufacturing Design for Manufacturing Lead H-PBGA Package Thermal Characteristics Thermal SolutionsThermal Recommendations Thermal ResistanceThis page left intentionally blank Related Documents ReferencesDesign References Design ReferencesElectronic Information Electronic InformationIntel 31244 PCI-X to Serial ATA Controller This page left intentionally blank