Cypress CY7C63310, CY7C638xx manual Instruction Set Summary

Page 12

CY7C63310, CY7C638xx

8. Instruction Set Summary

The instruction set is summarized in Table 8-1numerically and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the Cypress web site at http://www.cypress.com).

Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order[2, 3]

Opcode Hex

Cycles

Bytes

Instruction Format

Flags

Opcode Hex

Cycles

Bytes

Instruction Format

Flags

Opcode Hex

Cycles

Bytes

Instruction Format

Flags

 

 

 

 

 

 

 

 

 

00

15

1

SSC

 

2D

8

2

OR [X+expr], A

Z

5A

5

2

MOV [expr], X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

01

4

2

ADD A, expr

C, Z

2E

9

3

OR [expr], expr

Z

5B

4

1

MOV A, X

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

02

6

2

ADD A, [expr]

C, Z

2F

10

3

OR [X+expr], expr

Z

5C

4

1

MOV X, A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

03

7

2

ADD A, [X+expr]

C, Z

30

9

1

HALT

 

5D

6

2

MOV A, reg[expr]

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

04

7

2

ADD [expr], A

C, Z

31

4

2

XOR A, expr

Z

5E

7

2

MOV A, reg[X+expr]

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

05

8

2

ADD [X+expr], A

C, Z

32

6

2

XOR A, [expr]

Z

5F

10

3

MOV [expr], [expr]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

06

9

3

ADD [expr], expr

C, Z

33

7

2

XOR A, [X+expr]

Z

60

5

2

MOV reg[expr], A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

07

10

3

ADD [X+expr], expr

C, Z

34

7

2

XOR [expr], A

Z

61

6

2

MOV reg[X+expr], A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

08

4

1

PUSH A

 

35

8

2

XOR [X+expr], A

Z

62

8

3

MOV reg[expr], expr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

09

4

2

ADC A, expr

C, Z

36

9

3

XOR [expr], expr

Z

63

9

3

MOV reg[X+expr], expr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0A

6

2

ADC A, [expr]

C, Z

37

10

3

XOR [X+expr], expr

Z

64

4

1

ASL A

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0B

7

2

ADC A, [X+expr]

C, Z

38

5

2

ADD SP, expr

 

65

7

2

ASL [expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C

7

2

ADC [expr], A

C, Z

39

5

2

CMP A, expr

 

66

8

2

ASL [X+expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0D

8

2

ADC [X+expr], A

C, Z

3A

7

2

CMP A, [expr]

if (A=B) Z=1

67

4

1

ASR A

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0E

9

3

ADC [expr], expr

C, Z

3B

8

2

CMP A, [X+expr]

68

7

2

ASR [expr]

C, Z

if (A<B) C=1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0F

10

3

ADC [X+expr], expr

C, Z

3C

8

3

CMP [expr], expr

69

8

2

ASR [X+expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

4

1

PUSH X

 

3D

9

3

CMP [X+expr], expr

 

6A

4

1

RLC A

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

4

2

SUB A, expr

C, Z

3E

10

2

MVI A, [ [expr]++]

Z

6B

7

2

RLC [expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

6

2

SUB A, [expr]

C, Z

3F

10

2

MVI [ [expr]++], A

 

6C

8

2

RLC [X+expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

7

2

SUB A, [X+expr]

C, Z

40

4

1

NOP

 

6D

4

1

RRC A

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

7

2

SUB [expr], A

C, Z

41

9

3

AND reg[expr], expr

Z

6E

7

2

RRC [expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

8

2

SUB [X+expr], A

C, Z

42

10

3

AND reg[X+expr], expr

Z

6F

8

2

RRC [X+expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

9

3

SUB [expr], expr

C, Z

43

9

3

OR reg[expr], expr

Z

70

4

2

AND F, expr

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

10

3

SUB [X+expr], expr

C, Z

44

10

3

OR reg[X+expr], expr

Z

71

4

2

OR F, expr

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

5

1

POP A

Z

45

9

3

XOR reg[expr], expr

Z

72

4

2

XOR F, expr

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

4

2

SBB A, expr

C, Z

46

10

3

XOR reg[X+expr], expr

Z

73

4

1

CPL A

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1A

6

2

SBB A, [expr]

C, Z

47

8

3

TST [expr], expr

Z

74

4

1

INC A

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1B

7

2

SBB A, [X+expr]

C, Z

48

9

3

TST [X+expr], expr

Z

75

4

1

INC X

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1C

7

2

SBB [expr], A

C, Z

49

9

3

TST reg[expr], expr

Z

76

7

2

INC [expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1D

8

2

SBB [X+expr], A

C, Z

4A

10

3

TST reg[X+expr], expr

Z

77

8

2

INC [X+expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1E

9

3

SBB [expr], expr

C, Z

4B

5

1

SWAP A, X

Z

78

4

1

DEC A

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1F

10

3

SBB [X+expr], expr

C, Z

4C

7

2

SWAP A, [expr]

Z

79

4

1

DEC X

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

5

1

POP X

 

4D

7

2

SWAP X, [expr]

 

7A

7

2

DEC [expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

4

2

AND A, expr

Z

4E

5

1

SWAP A, SP

Z

7B

8

2

DEC [X+expr]

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

6

2

AND A, [expr]

Z

4F

4

1

MOV X, SP

 

7C

13

3

LCALL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

7

2

AND A, [X+expr]

Z

50

4

2

MOV A, expr

Z

7D

7

3

LJMP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

7

2

AND [expr], A

Z

51

5

2

MOV A, [expr]

Z

7E

10

1

RETI

C, Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

8

2

AND [X+expr], A

Z

52

6

2

MOV A, [X+expr]

Z

7F

8

1

RET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

9

3

AND [expr], expr

Z

53

5

2

MOV [expr], A

 

8x

5

2

JMP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

10

3

AND [X+expr], expr

Z

54

6

2

MOV [X+expr], A

 

9x

11

2

CALL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

11

1

ROMX

Z

55

8

3

MOV [expr], expr

 

Ax

5

2

JZ

 

29

4

2

OR A, expr

Z

56

9

3

MOV [X+expr], expr

 

Bx

5

2

JNZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2A

6

2

OR A, [expr]

Z

57

4

2

MOV X, expr

 

Cx

5

2

JC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2B

7

2

OR A, [X+expr]

Z

58

6

2

MOV X, [expr]

 

Dx

5

2

JNC

 

2C

7

2

OR [expr], A

Z

59

7

2

MOV X, [X+expr]

 

Ex

7

2

JACC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fx

13

2

INDEX

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

2.Interrupt routines take 13 cycles before execution resumes at interrupt vector table.

3.The number of cycles required by an instruction is increased by one for instructions that span 256 byte boundaries in the Flash memory space.

Document 38-08035 Rev. *K

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Contents Features ApplicationsCypress Semiconductor Corporation 198 Champion Court San Jose, CA Document 38-08035 Rev. *K Revised December 08Logic Block Diagram GpioIntroduction ConventionsPinouts Die Pad Summary Pad Number Pad Name Microns Pin Description Gpio Port 1 bit 0/USB D+ 1 If this pin is used as aGpio Port 1 bit 1/USB D- 1 If this pin is used as a CPU Architecture No connectSupply GroundCPU Registers Flags Register Addressing Modes Source Direct Opcode Operand Source Indexed Opcode Operand10. Destination Direct Opcode Operand Destination Indexed12. Destination Direct Source Immediate Opcode Operand 13. Destination Indexed Source Immediate Opcode Operand14. Destination Direct Source Direct Opcode Operand 15. Source Indirect Post Increment Opcode OperandInstruction Set Summary Instruction Set Summary Sorted Numerically by Opcode Order2Memory Organization Flash Program Memory OrganizationPOR/LVD INT0 EP0 EP1 EP2Data Memory Organization FlashSrom Stack begins here and grows upwardSrom Function Descriptions Srom Function Parameters Variable Name Sram AddressSrom Return Codes Description ReadBlock Parameters Name Address DescriptionProtection Modes Settings Description Marketing WriteBlock Parameters Name Address DescriptionEraseBlock Parameters Name Address Description Block Block nProtectBlock Parameters Name Address Description EraseAll Parameters Name Address Description10. Table Read Parameters Name Address Description 11. Return values for Table Read Table Number Return ValueSrom Table Clocking Checksum Function12. Checksum Parameters Name Address Description Clock Block Diagram Clock Architecture Description Iosc Trim Iosctr 0x34 R/WBit 40 Gain CPU/USB Clock Config Cpuclkcr 0x30 R/W Lposc Trim Lposctr 0x36 R/WBit 41 Reserved OSC Control 0 OSCCR0 0x1E0 R/W Bit 76 Reserved Bit 5 No BuzzUSB Osclock Clock Configuration Osclckcr 0x39 R/W Timer Clock Config Tmrclkcr 0x31 R/WBit 72 Reserved = TcapclkInterval Timer Clock Itmrclk Timer Capture Clock TcapclkCou nte r Terru pt Ntro ller Document 38-08035 Rev. *K CPU Clock During Sleep Mode Clock IO Config Clkiocr 0x32 R/WReset Sleep Mode Power on ResetWatchdog Timer Reset Reset Watchdog Timer Reswdt 0xE3 WSleep Sequence Wake up SequenceLow Power in Sleep Mode Wake Up TimingLow Voltage Detect Control Low Voltage Control Register Lvdcr 0x1E3 R/WBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM20 LVD Trip Point V Min Point V Typ Point V MaxVoltage Monitor Comparators Register Vltcmp 0x1E4 R Bit 72 Reserved Bit 1 LVDECO Trim Register ECO Ecotr 0x1EB R/WGeneral Purpose IO Gpio Ports Port Data RegistersP0 Data Register P0DATA0x00 R/W P1 Data Register P1DATA 0x01 R/W P2 Data Register P2DATA 0x02 R/WP3 Data Register P3DATA 0x03 R/W Gpio Port Configuration P0.0/CLKIN Configuration P00CR 0x05 R/W P0.1/CLKOUT Configuration P01CR 0x06 R/WP0.2/INT0-P0.4/INT2 Configuration P02CR-P04CR 0x07-0x09 R/W P0.5/TIO0 P0.6/TIO1 Configuration P05CR-P06CR 0x0A-0x0B R/WP0.7 Configuration P07CR 0x0C R/W 10. P1.0/D+ Configuration P10CR 0x0D R/W11. P1.1/D- Configuration P11CR 0x0E R/W 12. P1.2 Configuration P12CR 0x0F R/W13. P1.3 Configuration P13CR 0x10 R/W 14. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W15. P1.7 Configuration P17CR 0x14 R/W 16. P2 Configuration P2CR 0x15 R/W17. P3 Configuration P3CR 0x16 R/W Serial Peripheral Interface SPISPI Data Register SPI Data Register Spidata 0x3C R/WSPI Configure Register SPI Interface Pins SPI Mode Timing vs. LSB First, Cpol and CphaSclk Ssel DAT a Timer Registers Free Running Timer Low order Byte Frtmrl 0x20 R/WFree Running Timer High-order Byte Frtmrh 0x21 R/W RegistersTimer Capture 0 Rising TIO0R 0x22 R/W Timer Capture 1 Rising TIO1R 0x23 R/WTimer Capture 0 Falling TIO0F 0x24 R/W Timer Capture 1 Falling TIO1F 0x25 R/WProgrammable Interval Timer High Pitmrh 0x27 R Bit 74 ReservedProgrammable Interval Reload Low Pirl 0x28 R/W 10. Programmable Interval Reload High Pirh 0x29 R/WTimer Capture 11. Timer Configuration Tmrcr 0x2A R/WBit 20 Reserved 12. Capture Interrupt Enable Tcapinte 0x2B R/W 13. Capture Interrupt Status Tcapints 0x2C R/WTimer Functional Sequence Diagram Bit Free Running Counter Loading Timing Diagram Interrupt Controller Architectural DescriptionInterrupt Processing Interrupt Trigger ConditionsInterrupt Latency PCH PC158 is cleared to zeroInterrupt Registers Interrupt Clear 0 INTCLR0 0xDA R/WInterrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/WBit 7 Enable Software Interrupt Enswint Interrupt Mask 3 INTMSK3 0xDE R/WBit 60 Reserved Interrupt Mask 2 INTMSK2 0xDF R/W Interrupt Mask 1 INTMSK1 0xE1 R/W Interrupt Mask 0 INTMSK0 0xE0 R/W Interrupt Vector Clear Register Intvc 0xE2 R/WRegulator Output Vreg ControlVreg Control Register Vregcr 0x73 R/W USB Transceiver Configuration USB Transceiver Configure Register Usbxcr 0x74 R/WUSB/PS2 Transceiver USB Serial Interface Engine SIEUSB Device USB Device AddressEndpoint 0, 1, and 2 Count USB Device Address Usbcr 0x40 R/WEndpoint 0 Mode Endpoint 0 Mode EP0MODE 0x44 R/WBit 30 Mode Endpoint 1 and 2 Mode Endpoint 1 and 2 Mode EP1MODE EP2MODE 0x45, 0x46 R/WBit 7 Stall Endpoint 0 Data EP0DATA 0x50-0x57 R/WUSB Mode Tables Mode ColumnEncoding Column Endpoint 2 Data EP2DATA 0x60-0x67 R/WDetails of Mode for Differing Traffic Conditions SETUP, IN, and OUT ColumnsCount Fifo Addr Name Default Register SummaryTmrcr Intvc Voltage Vs CPU Frequency Characteristics Voltage vs CPU Frequency CharacteristicsDC Characteristics Absolute Maximum RatingsDetect 3V RegulatorAC Characteristics General Purpose IO InterfaceParameter Description Conditions Min Typical Max Unit Clock CpuclkNon-USB Mode Driver Characteristics USB Data TimingSPI Timing Gpio Timing Diagram Clock TimingDifferential Data Lines SCK CPOL=0 SCK CPOL=0 SCK CPOL=1 Ordering Information Package HandlingPackage Diagrams Pin 300-Mil Molded DIP P1Pin 300-Mil Molded DIP P3 Pin 300-Mil Soic S13 Pin QFN Package Document History Added block diagrams and timing diagrams Updated part numbers in the headerRemoved 638xx die diagram and die form pad assignment Removed Gpio port 4 configuration detailsVGT/AESA CMCC/PYRSSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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