Cypress CY7C63310, CY7C638xx Lposc Trim Lposctr 0x36 R/W, CPU/USB Clock Config Cpuclkcr 0x30 R/W

CY7C63310, CY7C638xx

Table 10-2. LPOSC Trim (LPOSCTR) [0x36] [R/W]

Bit #	7	6	5	4	3	2	1	0
Field	32 kHz Low	Reserved	32 kHz Bias Trim [1:0]			32 kHz Freq Trim [3:0]
	Power
Read/Write	R/W	–	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	D	D	D	D	D	D	D

This register is used to calibrate the 32 kHz Low speed Oscillator. The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing tests. This value does not require change during normal use. This is the meaning of ‘D’ in the Default field. If the 32 kHz Low power bit is written, care must be taken to not disturb the

32 kHz Bias Trim and the 32 kHz Freq Trim fields from their factory calibrated values. Bit 7: 32 kHz Low Power

0 = The 32 kHz Low speed Oscillator operates in normal mode

1 = The 32 kHz Low speed Oscillator operates in a low power mode. The oscillator continues to function normally, but with reduced accuracy.

Bit 6: Reserved

Bit [5:4]: 32 kHz Bias Trim [1:0]

These bits control the bias current of the low power oscillator.

0 0 = Mid bias

0 1 = High bias

1 0 = Reserved

1 1 = Reserved

Note Do not program the 32 kHz Bias Trim [1:0] field with the reserved 10b value because the oscillator does not oscillate at all corner conditions with this setting.

Bit [3:0]: 32 kHz Freq Trim [3:0]

These bits are used to trim the frequency of the low power oscillator.

Table 10-3. CPU/USB Clock Config (CPUCLKCR) [0x30] [R/W]

Bit #	7	6	5	4	3		2	1	0
Field	Reserved	USB CLK/2	USB CLK Select			Reserved			CPUCLK Select
		Disable
Read/Write	–	R/W	R/W	–	–		–	–	R/W
Default	0	0	0	0	0		0	0	0

Bit 7: Reserved

Bit 6: USB CLK/2 Disable

This bit only affects the USBCLK when the source is the external clock. When the USBCLK source is the Internal 24 MHz Oscillator, the divide by two is always enabled

0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24 MHz Oscillator is used, or when the external source is used with a 24 MHz clock

1 = USBCLK is undivided. Use this setting only with a 12 MHz external clock Bit 5: USB CLK Select

This bit controls the clock source for the USB SIE.

0 = Internal 24 MHz Oscillator. With the presence of USB traffic, the Internal 24 MHz Oscillator is trimmed to meet the USB requirement of 1.5% tolerance (see Table 10-5on page 24)

1 = External clock—Internal Oscillator is not trimmed to USB traffic. Proper USB SIE operation requires a 12 MHz or 24 MHz clock accurate to <1.5%.

Bit [4:1]: Reserved

Bit 0: CPU CLK Select

0 = Internal 24 MHz Oscillator.

1 = External clock—External clock at CLKIN (P0.0) pin.

Note The CPU speed selection is configured using the OSC_CR0 Register (Table 10-4on page 23).

Document 38-08035 Rev. *K Page 22 of 83

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