CY7C63310, CY7C638xx
32. Document History Page (continued)
Document Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller
Document Number:
Rev. | ECN No. | Orig. of | Submission | Description of Change | |
Change | Date | ||||
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*G | 424790 | TYJ | See ECN | Minor text changes to make document more readable | |
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| Removed CY7C639xx | |
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| Removed CY7C639xx from Ordering Information on page 75 | |
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| Added text concerning current draw for P0.0 and P0.1 in Table | |
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| Corrected Figure | |
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| Added comment about availability of 3.3V IO on | |
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| 6 | |
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| Added information on Flash endurance and data retention to section Flash on | |
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| page 14 | |
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| Added block diagrams and timing diagrams | |
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| Added CY7C638xx die form diagrams, Pad assignment tables and Ordering | |
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| information | |
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| Keyboard references removed | |
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| Updated part numbers in the header | |
*H | 491711 | TYJ | See ECN | Minor text changes | |
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| Removed 638xx die diagram and die form pad assignment | |
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| Removed GPIO port 4 configuration details | |
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| Corrected GPIO characteristics of P0.0 and P0.1 to P1.0 and P1.1 respectively | |
*I | 504691 | TYJ | See ECN | Minor text changes | |
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| Removed all residual references to external crystal oscillator and GPIO4 | |
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| Documented the dedicated 3.3V regulator for USB transceiver | |
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| Documented bandgap/voltage regulator behavior on wake up | |
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| Voltage regulator line/load regulation documented | |
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| USB Active and PS2 Data low interrupt trigger conditions documented. | |
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| GPIO capacitance and timing diagram included | |
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| Method to clear Capture Interrupt Status bit discussed | |
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| Sleep and Wake up sequence documented. | |
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| EP1MODE/EP2MODE register issue discussed. |
Document | Page 81 of 83 |
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